Investigation of Critical Interfaces of Transition Metal Dichalcogenide Devices for Future Device Applications

dc.contributor.advisorYoung, Chadwin D.
dc.creatorBolshakov, Pavel
dc.creator.orcid0000-0002-6098-6823
dc.date.accessioned2021-12-15T21:21:27Z
dc.date.available2021-12-15T21:21:27Z
dc.date.created2019-12
dc.date.issued2019-11-18
dc.date.submittedDecember 2019
dc.date.updated2021-12-15T21:21:28Z
dc.description.abstractRecently, transition metal dichalcogenides (TMDs) have drawn significant attention due to their two-dimensional structure and unique properties that show the potential for applications in various devices such as transistors, solar cells, and sensors. Initial TMD devices have demonstrated promising results in terms of device performance. However, the high contact resistance and Fermi level pinning at the contact metal – TMD interface prevents efficient carrier injection in electronic devices. Furthermore, the interactions at the bottom-gate high-κ dielectric – TMD interface and at the top-gate high-κ dielectric – TMD interface have not been sufficiently studied using I-V analysis. In this dissertation, device fabrication, physical and electrical characterization, and enhanced device analysis of dual-gate MoS2 field-effect-transistors are demonstrated with a focus on the critical interfaces. Bottom-gate MoS2 transistors and capacitors with high-κ dielectrics are characterized using I-V and C-V measurements to determine the influence of the bottom-gate dielectric on top-gate transistor performance. Electrical characterization through the dual-gate transistor fabrication process is done to determine the type of charge HfO2 introduces on the top MoS2 surface compared to Al2O3/HfO2 bilayer. Dual-gate sweeping methodology is introduced to TMD transistors in order to understand the influence of the top-gate dielectric compared to the bottom-gate dielectric on device performance. An oxygen plasma clean is used during device contact patterning to functionalize the MoS2 surface to de-pin the Fermi level and allow for low contact resistance formation. Low contact resistance combined with high quality high-κ dielectric gate stacks in conjunction with dual-gate sweeping is studied. Devices with sub-thermionic transport are observed and enhanced I-V analysis and modeling is done to determine the potential origins of the sub-60 mV/dec phenomenon. The electrical and physical characterization and analysis of critical interfaces of TMD devices in this dissertation provides insights into the interfacial influence on device performance and the origins of any defects present.
dc.format.mimetypeapplication/pdf
dc.identifier.urihttps://hdl.handle.net/10735.1/9361
dc.language.isoen
dc.subjectTwo-dimensional materials
dc.subjectInterfaces (Physical sciences)
dc.subjectTransistors
dc.titleInvestigation of Critical Interfaces of Transition Metal Dichalcogenide Devices for Future Device Applications
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentMaterials Science and Engineering
thesis.degree.grantorThe University of Texas at Dallas
thesis.degree.levelDoctoral
thesis.degree.namePHD

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