Zhai, J.Yan, C.Wang, S. -GZhou, Dian2019-07-122019-07-122018-06-249781450357005https://hdl.handle.net/10735.1/6704Full text access from Treasures at UT Dallas is restricted to current UTD affiliates (use the provided Link to Article). Non UTD affiliates will find the web address for this item by clicking the "Show full item record" link, copying the "dc.relation.uri" metadata and pasting it into a browser.With increasing dimension of variation space and computational intensive circuit simulation, accurate and fast yield estimation of realistic SRAM chip remains a significant and complicated challenge. In this paper, du Experiment results show that the proposed method has an almost constant time complexity as the dimension increases, and gains 6x speedup over the state-of-the-art method in the 485D cases.en©2018 Association for Computing MachineryComputer-aided designTiming circuitsBayesian statistical decision theorySRAM (Static random access memory)Integrated circuits--Computer simulationElectronic circuits--Computer simulationarticleZhai, J., C. Yan, S. -G Wang, and D. Zhou. 2018. "An efficient bayesian yield estimation method for high dimensional and high sigma SRAM circuits." Proceedings - Design Automation Conference, 55, vol. 137710: art. 132, doi:10.1145/3195970.3195987137710