Zhou, H.Zhu, H.Cui, T.Pan, D. Z.Zhou, D.Zeng, X.2019-07-262019-07-262018-07-052156-3950https://hdl.handle.net/10735.1/6736Full text access from Treasures at UT Dallas is restricted to current UTD affiliates (use the provided Link to Article). Non UTD affiliates will find the web address for this item by clicking the "Show full item record" link, copying the "dc.relation.uri" metadata and pasting it into a browser.Drop test is usually adopted in the integrated circuit (IC) testing to estimate the shock resistance capability of IC packaging. Generally, it is very time consuming for the drop test simulation, therefore, the fast numerical approach is generally needed to reduce the computational cost. In this paper, we propose an efficient drop-test simulator for through-siliconvia (TSV) based three-dimensional integrated circuit (3D IC) to simulate its mechanical behaviors under drop impact. The proposed simulator is based on the idea of domain decomposition (DD) to improve the condition number of the coefficient matrix of the solver. We further develop two efficient numerical techniques in the simulator to improve its efficiency. First, a second order formulation is proposed for the initial solution selection in preconditioned conjugate gradient (PCG) solver, which can efficiently reduce the number of PCG iterations at each time point during simulation. And second, an equivalent structureembedded model is proposed and applied in the first Schwarz iteration to efficiently reduce the number of Schwarz iterations in DD method. Numerical experiments show that the proposed drop-test simulator can achieve 7.03× speedup in comparison with the conventional FEM-based solver. It is demonstrated in the paper in the paper through several examples with multi chip layers, of which each chip layer consists of an 8 × 8 TSV array, that the proposed simulator can be widely applied to reliability analysis of 3D ICs under drop impact.en©2018 IEEEReliabilityChip scale packagingIntegrated circuits—Design and constructionIntegrated circuitsIterative methods (Mathematics)Number theoryAccelerated life testingSimulation methodsTiming circuitsThree-dimensional integrated circuitsarticleZhou, H., H. Zhu, T. Cui, D. Z. Pan, et al. 2018. "An improved domain decomposition method for drop impact reliability analysis of 3d ICs." IEEE Transactions on Components, Packaging and Manufacturing Technology 8(10): 1788-1799, doi:10.1109/TCPMT.2018.2853157810