Wang, ZiSchaefer, Benjamin Carrion2020-03-312020-03-312019-039783981926323http://dx.doi.org/10.23919/DATE.2019.8714920https://hdl.handle.net/10735.1/7731Due to copyright restrictions and/or publisher's policy full text access from Treasures at UT Dallas is limited to current UTD affiliates (use the provided Link to Article).Commercial High-Level Synthesis (HLS) tool vendors have started to enable ways to protect Behavioral IP (BIPs) from being unlawful used. The main approach is to provide tools to encrypt these BIPs which can be decrypted by the HLS tool only. The main problem with this approach is that encrypting the IP does not allow BIP users to insert synthesis directives into the source code in the form of pragmas (comments), and hence cancels out one of the most important advantages of C-based VLSI design: The ability to automatically generate micro-architectures with unique design metrics, e.g. area, power and performance. This work studies the impact to the search space when synthesis directives are not able to be inserted in to the encrypted IP source code while other options are still available to the BIP users (e.g. setting global synthesis options and limiting the number and type of functional units) and proposes a method that selectively controls the search space by encrypting different portions of the BIP. To achieve this goal we propose a fast heuristic based on divide and conquer method. Experimental results show that our proposed method works well compared to an exhaustive search that leads to the optimal solution. © 2019 EDAA.en©2019 EDAAC (Computer program language)Computer architectureCryptographyHeuristic programmingMicro Channel (Computer bus)Integrated circuits--Design and constructionIntegrated circuits--Very large scale integrationOuter space—ExplorationPartial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level SynthesisarticleWang, Z., and B. C. Schafer. 2019. "Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis." Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition: 642-645, doi: 10.23919/DATE.2019.8714920