Taher, Farah NazJoslin, MatthewBalachandran, A.Zhu, ZhiqiSchaefer, Benjamin Carrion2020-03-302020-03-302019-03-259783981926323http://dx.doi.org/10.23919/DATE.2019.8714816https://hdl.handle.net/10735.1/7692Due to copyright restrictions and/or publisher's policy full text access from Treasures at UT Dallas is limited to current UTD affiliates (use the provided Link to Article).Fault tolerance is vital in many domains. One popular way to increase fault-tolerance is through hardware redundancy. However, basic redundancy cannot cope with Common Mode Failures (CMFs). One way to address CMF is through the use of diversity in combination with traditional hardware redundancy. This work proposes an automatic design space exploration (DSE) method to generate optimized redundant hardware accelerators with maximum diversity to protect against CMFs given as a single behavioral description for High-Level Synthesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over the traditional RT-level design based on low-level Hardware Description Languages (HDLs): The ability to generate micro-architectures with unique characteristics from the same behavioral description. Experimental results show that the proposed method provides a significant diversity increment compared to using traditional RTL-based exploration to generate diverse designs. © 2019 EDAA.en©2019 EDAAC (Computer program language)Computer architectureComputer hardware description languagesFault-tolerant computingRedundancy (Engineering)Level design (Computer science)Microcomputers--Design and constructionIntegrated circuits—Very large scale integrationarticleTaher, F. N., M. Joslin, A. Balachandran, Z. Zhu, et al. 2019. "Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis." Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition: 1563-1566, doi: 10.23919/DATE.2019.8714816