Browsing by Author "Zhu, Zhiqi"
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Item Common-Mode Failure Mitigation: Increasing Diversity Through High-Level Synthesis(Institute of Electrical and Electronics Engineers Inc., 2019-03-25) Taher, Farah Naz; Joslin, Matthew; Balachandran, A.; Zhu, Zhiqi; Schaefer, Benjamin Carrion; Taher, Farah Naz; Joslin, Matthew; Zhu, Zhiqi; Schaefer, Benjamin CarrionFault tolerance is vital in many domains. One popular way to increase fault-tolerance is through hardware redundancy. However, basic redundancy cannot cope with Common Mode Failures (CMFs). One way to address CMF is through the use of diversity in combination with traditional hardware redundancy. This work proposes an automatic design space exploration (DSE) method to generate optimized redundant hardware accelerators with maximum diversity to protect against CMFs given as a single behavioral description for High-Level Synthesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over the traditional RT-level design based on low-level Hardware Description Languages (HDLs): The ability to generate micro-architectures with unique characteristics from the same behavioral description. Experimental results show that the proposed method provides a significant diversity increment compared to using traditional RTL-based exploration to generate diverse designs. © 2019 EDAA.Item Reducing the Complexity of Fault-Tolerant Behavioral Hardware Accelerators(2020-08) Zhu, Zhiqi; Schaefer, Benjamin CarrionContinuous technology scaling has allowed to integrate a large number of different hardware components on the same integrated circuit (IC). Thus, these complex ICs are typically called System-on-Chip (SoC). Area, power and performance have been traditionally the most important design metrics, but for many safety critical applications, reliability is equally important. Fault tolerance can therefore not be a second class citizen anymore and must be considered early on in the design process of these complex ICs. Due to the heterogeneity of these SoCs a single fault-tolerance solution is not possible. Dedicated solutions have been proposed for the embedded processor, the memory, different interfaces and for the dedicated hardware accelerators. For example, in the processor case, the program execution relies on the control flow instructions that determine which section of code will be executed at run-time. A single event upset (SEU) can impact the execution order of the program. Thus, in this thesis we study the effect of transient errors on the corruption of program control flows, and present a methodology to detect these at the software level. This is done by inserting additional control flow instructions directly at the assembly code after a static control flow analysis is performed. Moreover, one key differentiating element between different SoCs is the hardware accelerators in them. Most of other components in the SoCs are off-the-shelve modules and the main differentiation element in the different SoC offering is typically the mix of hardware accelerators that they include. Due to the long design cycles of these complex systems, the design of these accelerators is often now done at the behavioral level and High-Level Synthesis (HLS) is used to generate the Register Transfer Level (RTL) code of the accelerator. It is therefore imperative to introduce low overhead fault-tolerance techniques for these accelerators described at the behavioral level. This thesis presents different techniques to reduce the overhead associated with traditional N-modular redundancy techniques for these accelerators.