Common-Mode Failure Mitigation: Increasing Diversity Through High-Level Synthesis

Date

2019-03-25

Authors

Taher, Farah Naz
Joslin, Matthew
Balachandran, A.
Zhu, Zhiqi
Schaefer, Benjamin Carrion

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Publisher

Institute of Electrical and Electronics Engineers Inc.

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Abstract

Fault tolerance is vital in many domains. One popular way to increase fault-tolerance is through hardware redundancy. However, basic redundancy cannot cope with Common Mode Failures (CMFs). One way to address CMF is through the use of diversity in combination with traditional hardware redundancy. This work proposes an automatic design space exploration (DSE) method to generate optimized redundant hardware accelerators with maximum diversity to protect against CMFs given as a single behavioral description for High-Level Synthesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over the traditional RT-level design based on low-level Hardware Description Languages (HDLs): The ability to generate micro-architectures with unique characteristics from the same behavioral description. Experimental results show that the proposed method provides a significant diversity increment compared to using traditional RTL-based exploration to generate diverse designs. © 2019 EDAA.

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Keywords

C (Computer program language), Computer architecture, Computer hardware description languages, Fault-tolerant computing, Redundancy (Engineering), Level design (Computer science), Microcomputers--Design and construction, Integrated circuits—Very large scale integration

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Rights

©2019 EDAA

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