Common-Mode Failure Mitigation: Increasing Diversity Through High-Level Synthesis

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dc.contributor.authorTaher, Farah Naz
dc.contributor.authorJoslin, Matthew
dc.contributor.authorBalachandran, A.
dc.contributor.authorZhu, Zhiqi
dc.contributor.authorSchaefer, Benjamin Carrion
dc.contributor.utdAuthorTaher, Farah Naz
dc.contributor.utdAuthorJoslin, Matthew
dc.contributor.utdAuthorZhu, Zhiqi
dc.contributor.utdAuthorSchaefer, Benjamin Carrion
dc.date.accessioned2020-03-30T21:12:17Z
dc.date.available2020-03-30T21:12:17Z
dc.date.issued2019-03-25
dc.descriptionDue to copyright restrictions and/or publisher's policy full text access from Treasures at UT Dallas is limited to current UTD affiliates (use the provided Link to Article).
dc.description.abstractFault tolerance is vital in many domains. One popular way to increase fault-tolerance is through hardware redundancy. However, basic redundancy cannot cope with Common Mode Failures (CMFs). One way to address CMF is through the use of diversity in combination with traditional hardware redundancy. This work proposes an automatic design space exploration (DSE) method to generate optimized redundant hardware accelerators with maximum diversity to protect against CMFs given as a single behavioral description for High-Level Synthesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over the traditional RT-level design based on low-level Hardware Description Languages (HDLs): The ability to generate micro-architectures with unique characteristics from the same behavioral description. Experimental results show that the proposed method provides a significant diversity increment compared to using traditional RTL-based exploration to generate diverse designs. © 2019 EDAA.
dc.description.departmentErik Jonsson School of Engineering and Computer Science
dc.identifier.bibliographicCitationTaher, F. N., M. Joslin, A. Balachandran, Z. Zhu, et al. 2019. "Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis." Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition: 1563-1566, doi: 10.23919/DATE.2019.8714816
dc.identifier.isbn9783981926323
dc.identifier.urihttp://dx.doi.org/10.23919/DATE.2019.8714816
dc.identifier.urihttps://hdl.handle.net/10735.1/7692
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.relation.isPartOfProceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition
dc.rights©2019 EDAA
dc.subjectC (Computer program language)
dc.subjectComputer architecture
dc.subjectComputer hardware description languages
dc.subjectFault-tolerant computing
dc.subjectRedundancy (Engineering)
dc.subjectLevel design (Computer science)
dc.subjectMicrocomputers--Design and construction
dc.subjectIntegrated circuits—Very large scale integration
dc.titleCommon-Mode Failure Mitigation: Increasing Diversity Through High-Level Synthesis
dc.type.genrearticle

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