Young, Chadwin D.

Permanent URI for this collectionhttps://hdl.handle.net/10735.1/4400

Chadwin Young is an Assistant Professor of Materials Science and Engineering. His research interests include:

Electrical Characterization Methodologies
Reliability Characterization Methodologies
Solid State Device Physics
Electrical properties of materials
MOS modeling (quantum effects, etc.)
Nanotechnology
Flexible Electronics
Future Energy Needs (Renewable, low power operation, etc.)

ORCID page

Browse

Now showing 1 - 10 of 10

A Multifield and Frequency Electrically Detected Magnetic Resonance Study of Atomic-Scale Defects in Gamma Irradiated Modern MOS Integrated Circuitry
(IEEE-Institute of Electrical and Electronics Engineers Inc, 2018-11-09) Myers, K. J.; Waskiewicz, R. J.; Lenahan, P. M.; Young, Chadwin D.; 0000-0003-0690-7423 (Young, CD); Young, Chadwin D.
The role of specific atomic-scale defects involved in total ionizing dose radiation in the metal-oxide-semiconductor field-effect transistors of the 1980s and 1990s was identified in large part with electron paramagnetic resonance (EPR) techniques. The techniques involved in those studies were classical EPR and, to a lesser extent, electrically detected magnetic resonance (EDMR). We show that somewhat more sophisticated resonance-based measurements can be fruitfully applied to explore the atomic-scale basic mechanisms of the significantly more complex, generally messier, and much smaller devices of the present day. We present multifield and frequency EDMR measurements in which the response is observed via spin-dependent leakage currents, spin-dependent charge pumping, and spin-dependent gated diode recombination currents. We also exploit isotopic substitution, replacing hydrogen with deuterium, monitoring the isotopic effects on the resonance response. The approaches utilized in this paper should be applicable to radiation damage studies in a wide variety of emerging materials and devices.
A New Analytical Tool for the Study of Radiation Effects in 3-D Integrated Circuits: Near-Zero Field Magnetoresistance Spectroscopy
(Institute of Electrical Electronics Engineers Inc, 2018-12-06) Ashton, James P.; Moxim, Stephen J.; Lenahan, Patrick M.; McKay, Colin G.; Waskiewicz, Ryan J.; Myers, Kenneth J.; Flatte, Michael E.; Harmon, Nicholas J.; Young, Chadwin D.; 0000-0003-0690-7423 (Young, CD); Young, Chadwin D.
We demonstrate that a new technique, near-zero field magnetoresistance (NZFMR) spectroscopy, can explore radiation damage in a wide variety of devices in a proof-of-concept study. The technique has great potential for the study of atomic-scale mechanisms of radiation damage in 3-D integrated circuits. In our study, we explore radiation damage in structures relevant to 3-D integrated circuits, but not on 3-D test structures themselves. Five structures of great technological importance to 3-D integrated circuits are investigated. We utilize both NZFMR and electrically detected magnetic resonance to investigate radiation effects in these structures. The structures involved in this paper are planar silicon metal-oxide-semiconductor field-effect transistors, silicon-germanium alloy-based transistors, fin-based transistors, silicon dioxide-based flowable oxides, and low-k dielectrics. Our study indicates that NZFMR has great potential in radiation damage studies, with exceptional promise in systems in which more conventional resonance is not possible.
Dual-Gate MoS₂ Transistors with Sub-10 NM Top-Gate High-K Dielectrics
(American Institute of Physics Inc.) Bolshakov, Pavel; Khosravi, Ava; Zhao, Peng; Hurley, P. K.; Hinkle, Christopher L.; Wallace, Robert M.; Young, Chadwin D.; 0000-0002-3530-6400 (Zhao, P); 0000-0001-5566-4806 (Wallace, RM); 0000-0003-0690-7423 (Young, CD); Bolshakov, Pavel; Khosravi, Ava; Zhao, Peng; Hinkle, Christopher L.; Wallace, Robert M.; Young, Chadwin D.
High quality sub-10 nm high-k dielectrics are deposited on top of MoS₂ and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO₂ and an Al₂O₃/HfO₂ bilayer shows significant improvement in device performance due to the insertion of the thin Al₂O₃ layer. The results show that the Al₂O₃ buffer layer improves the interface quality by effectively reducing the net fixed positive oxide charge at the top-gate MoS₂/high-k dielectric interface. Dual-gate sweeping, where both the top-gate and the back-gate are swept simultaneously, provides significant insight into the role of these oxide charges and improves overall device performance. Dual-gate transistors encapsulated in an Al₂O₃ dielectric demonstrate a near-ideal subthreshold swing of ~60 mV/dec and a high field effect mobility of 100 cm²/V·s.
Effect of Film Thickness on the Ferroelectric and Dielectric Properties of Low-Temperature (400 ⁰C) Hf₀.₅Zr₀.₅O₂ Films
(American Institute of Physics) Kim, Si Joon; Mohan. Jaidah; Lee, Jaebeom; Lee, Joy S.; Lucero, Antonion T.; Young, Chandwin D.; Colombo, Luigi; Summerfelt, Scott R.; San, Tamer; Kim, Jiyoung; Kim, Si Joon; Mohan. Jaidah; Lee, Jaebeom; Lee, Joy S.; Lucero, Antonion T.; Young, Chandwin D.; Colombo, Luigi; Kim, Jiyoung
We report on the effect of the Hf₀.₅Zr₀.₅O₂ (HZO) film thickness on the ferroelectric and dielectric properties using pulse write/read measurements. HZO films of thicknesses ranging from 5 to 20 nm were annealed at 400 ⁰C for 1min in a nitrogen ambient to be compatible with the back-end of the line thermal budget. As the HZO film thickness decreases, low-voltage operation (1.0V or less) can be achieved without the dead layer effect, although switching polarization (P_{sw}) tends to decrease due to the smaller grain size. Meanwhile, for 20-nm-thick HZO films prepared under the identical stress (similar TiN top electrode thickness and thermal budget), the P_{sw} and dielectric constant are reduced because of additional monoclinic phase formation.
Electrical Characterization of the Temperature Dependence in CdTe/CdS Heterojunctions Deposited In-Situ by Pulsed Laser Deposition
(American Institute of Physics Inc) Avila-Avendano, Jesus Alberto; Quevedo-López, Manuel A.; Young, Chadwin D.; 0000-0003-0690-7423 (Young, CD); Avila-Avendano, Jesus Alberto; Quevedo-López, Manuel A.; Young, Chadwin D.
The I-V and C-V characteristics of CdTe/CdS heterojunctions deposited in-situ by Pulsed Laser Deposition (PLD) were evaluated. In-situ deposition enables the study of the CdTe/CdS interface by avoiding potential impurities at the surface and interface as a consequence of exposure to air. The I-V and C-V characteristics of the resulting junctions were obtained at different temperatures, ranging from room temperature to 150 °C, where the saturation current (from 10⁻⁸ to 10⁻⁴A/cm²), ideality factor (between 1 and 2), series resistance (from 10² to 10⁵ Ω), built-in potential (0.66-0.7 V), rectification factor (∼10⁶), and carrier concentration (∼10¹⁶ cm⁻³) were obtained. The current-voltage temperature dependence study indicates that thermionic emission is the main transport mechanism at the CdTe/CdS interface. This study also demonstrated that the built-in potential (V_{bi}) calculated using a thermionic emission model is more accurate than that calculated using C-V extrapolation since C-V plots showed a V_{bi} shift as a function of frequency. Although CdTe/CdS is widely used for photovoltaic applications, the parameters evaluated in this work indicate that CdTe/CdS heterojunctions could be used as rectifying diodes and junction field effect transistors (JFETs). JFETs require a low PN diode saturation current, as demonstrated for the CdTe/CdS junction studied here. © 2018 Author(s).
Engineering The Palladium-WSe₂ Interface Chemistry for Field Effect Transistors with High-Performance Hole Contacts
(Amer Chemical Soc, 2018-12-07) Smyth, Christopher M.; Walsh, Lee A.; Bolshakov, Pavel; Catalano, Massimo; Addou, Rafik; Wang, Luhua; Kim, Jiyoung; Kim, Moon J.; Young, Chadwin D.; Hinkle, Christopher L.; Wallace, Robert M.; 0000-0001-5566-4806 (Wallace, RM); 0000-0003-0690-7423 (Young, CD); 0000-0003-2781-5149 (Kim, J); 0000-0002-6688-8626 (Walsh, LA); 0000-0002-5485-6600 (Hinkle, CD); 0000-0002-5454-0315 (Addou, R); 70133685 (Kim, J); Smyth, Christopher M.; Walsh, Lee A.; Bolshakov, Pavel; Catalano, Massimo; Addou, Rafik; Wang, Luhua; Kim, Jiyoung; Kim, Moon J.; Young, Chadwin D.; Hinkle, Christopher L.; Wallace, Robert M.
Palladium has been widely employed as a hole contact to WSe₂ and has enabled, at times, the highest WSe₂ transistor performance. However, there are orders of magnitude variation across the literature in Pd-WSe₂ contact resistance and I-ON/I-OFF ratios with no true understanding of how to consistently achieve high-performance contacts. In this work, WSe₂ transistors with impressive I-ON/I-OFF ratios of 10(6) and Pd-WSe₂ Schottky diodes with near-zero variability are demonstrated utilizing Ohmic-like Pd contacts through deliberate control of the interface chemistry. The increased concentration of a PdSeₓ intermetallic is correlated with an Ohmic band alignment and concomitant defect passivation, which further reduces the contact resistance, variability, and barrier height inhomogeneity. The lowest contact resistance occurs when a 60 min post-metallization anneal at 400 degrees C in forming gas (FG) is performed. X-ray photoelectron spectroscopy indicates this FG anneal produces 3x the concentration of PdSeₓ and an Ohmic band alignment, in contrast to that detected after annealing in ultrahigh vacuum, during which a 0.2 eV hole Schottky barrier forms. Raman spectroscopy and scanning transmission electron microscopy highlight the necessity of the fabrication step to achieve high-performance contacts as no PdSeₓ forms, and WSe₂ is unperturbed by room temperature Pd deposition. However, at least one WSe₂ layer is consumed by the necessary interface reactions that form PdSeₓ requiring strategic exploitation of a sacrificial WSe₂ layer during device fabrication. The interface chemistry and structural properties are correlated with Pd-WSe₂ diode and transistor performance, and the recommended processing steps are provided to enable reliable high-performance contact formation.
Ferroelectric TiN/Hf₀.₅Zr₀.₅O₂/Tin Capacitors with Low-Voltage Operation and High Reliability for Next-Generation FRAM Applications
(Institute of Electrical and Electronics Engineers Inc.) Kim, Si Joon; Mohan, Jaidah; Young, Chadwin D.; Colombo, Luigi; Kim, Jiyoung; Summerfelt, S. R.; San, T.; 0000-0003-0690-7423 (Young, CD); 0000-0003-2781-5149 (Kim, J); 70133685 (Kim, J); Kim, Si Joon; Mohan, Jaidah; Young, Chadwin D.; Colombo, Luigi; Kim, Jiyoung
In this study, we investigated the ferroelectric properties of Hf₀.₅Zr₀.₅O₂ (HZO) thin films with different thicknesses (5-20 nm) deposited by atomic layer deposition for the development of future ferroelectric random access memory cells. HZO-based capacitors with a thickness of 5 nm exhibited a switching polarization of ~13 μC/cm² and a ferroelectric saturation voltage of 1.0 V as extracted from the pulse write/read measurements. Furthermore, we performed fatigue measurements and we found no degradation up to 10¹⁰ switching cycles at 1.2 V.
Investigation of Negative Bias Temperature Instability Dependence on Fin Width of Silicon-On-Insulator-Fin-Based Field Effect Transistors
Young, Chadwin D.; Neugroschel, Arnost; Majumdar, Kausik; Matthews, Ken; Wang, Zhe; Hobbs, Chris; Young, Chadwin D.; Neugroschel, Arnost; Majumdar, Kausik; Matthews, Ken; Wang, Zhe; Hobbs, Chris
The fin width dependence of negative bias temperature instability (NBTI) of double-gate, fin-based p-type Field Effect Transistors (FinFETs) fabricated on silicon-on-insulator (SOI) wafers was investigated. The NBTI degradation increased as the fin width narrowed. To investigate this phenomenon, simulations of pre-stress conditions were employed to determine any differences in gate oxide field, fin band bending, and electric field profile as a function of the fin width. The simulation results were similar at a given gate stress bias, regardless of the fin width, although the threshold voltage was found to increase with decreasing fin width. Thus, the NBTI fin width dependence could not be explained from the pre-stress conditions. Different physics-based degradation models were evaluated using specific fin-based device structures with different biasing schemes to ascertain an appropriate model that best explains the measured NBTI dependence. A plausible cause is an accumulation of electrons that tunnel from the gate during stress into the floating SOI fin body. As the fin narrows, the sidewall device channel moves in closer proximity to the stored electrons, thereby inducing more band bending at the fin/dielectric interface, resulting in a higher electric field and hole concentration in this region during stress, which leads to more degradation. The data obtained in this work provide direct experimental proof of the effect of electron accumulation on the threshold voltage stability in FinFETs.
Positive Bias Instability in ZnO TFTs with Al₂O₃ Gate Dielectric
(Institute of Electrical and Electronics Engineers Inc., 2019-03-31) Bolshakov, Pavel; Rodriguez-Davila, Rodolfo A.; Quevedo-López, Manuel A.; Young, Chadwin D.; 0000-0003-0690-7423 (Young, CD); Bolshakov, Pavel; Rodriguez-Davila, Rodolfo A.; Quevedo-López, Manuel A.; Young, Chadwin D.
Positive bias instability stress (PBI) was done on ZnO thin-film transistors (TFTs) with Al₂O₃ deposition at 100°C and 250°C. The threshold voltage (VT), transconductance (g ₘ), and subthreshold slope (SS) were monitored where the 100°C samples demonstrated a 'turn-around' phenomenon in the ΔVₜ compared to the 250°C samples. The 250°C samples show consistent ΔVₜ, suggesting a higher Al₂O₃ deposition temperature results in the absence of the defect responsible for the 'turn-around' effect. Both sets also demonstrate negligible degradation in Δgₘ and ASS -suggesting little to no influence on the Vₜ shift by interfacial state generation. © 2019 IEEE.
Sensitivity of High-k Encapsulated MoS₂ Transistors to I-V Measurement Execution Time
(Institute of Electrical and Electronics Engineers Inc.) Bolshakov, Pavel; Khosravi, Ava; Zhao, Peng; Wallace, Robert M.; Young, Chadwin D.; Hurley, P. K.; Bolshakov, Pavel; Khosravi, Ava; Zhao, Peng; Wallace, Robert M.; Young, Chadwin D.
High-k encapsulated MoS₂ field-effect-transistors were fabricated and electrically characterized. Comparison between HfO₂ and Al₂O₃ encapsulated MoS₂ FETs and their I-V response to execution time are shown. Changes in gate voltage step and integration time demonstrate that electrical characterization parameters can significantly impact device parameters such as the subthreshold swing and the threshold voltage. © 2018 IEEE.

Browse

Browsing Young, Chadwin D. by Title