Lee, Mark

Permanent URI for this collectionhttps://hdl.handle.net/10735.1/4259

Mark Lee is a Professor of physics as well as the department's Associate Head. His main areas of research involve:

  • Experimental solid-state physics,
  • Materials physics or
  • Electronic and photonics device physics
    • .
He is specifically interested in "quantum effects in novel materials, nanomaterials, and devices, especially the response to microwave through terahertz electromagnetic fields."

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    Microwave Conductance of Aligned Multiwall Carbon Nanotube Textile Sheets
    (2014-12-30) Brown, Brian L.; Bykova, Julia S.; Howard, Austin R.; Zakhidov, Anvar A.; Shaner, Eric A.; Lee, Mark; Brown, Brian L.; Bykova, Julia S.; Howard, Austin R.; Zakhidov, Anvar A.; Lee, Mark
    Multiwall carbon nanotube (MWNT) sheets are a class of nanomaterial-based multifunctional textile with potentially useful microwave properties. To understand better the microwave electrodynamics, complex AC conductance measurements from 0.01 to 50 GHz were made on sheets of highly aligned MWNTs with the alignment texture both parallel and perpendicular to the microwave electric field polarization. In both orientations, the AC conductance is modeled to first order by a parallel frequency-independent conductance and capacitance with no inductive contribution. This is consistent with low-frequency diffusive Drude AC conduction up to 50 GHz, in contrast to the "universal disorder" AC conduction reported in many types of single-wall nanotube materials.
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    Negative Differential Transconductance in Silicon Quantum Well Metal-Oxide-Semiconductor Field Effect/Bipolar Hybrid Transistors
    (American Institute Of Physics Inc., 2014-11-25) Naquin, Clint; Lee, Mark; Edwards, H.; Mathur, G.; Chatterjee, T.; Maggio, K.
    Introducing explicit quantum transport into Si transistors in a manner amenable to industrial fabrication has proven challenging. Hybrid field-effect/bipolar Si transistors fabricated on an industrial 45 nm process line are shown to demonstrate explicit quantum transport signatures. These transistors incorporate a lateral ion implantation-defined quantum well (QW) whose potential depth is controlled by a gate voltage (VG). Quantum transport in the form of negative differential transconductance (NDTC) is observed to temperatures > 200 K. The NDTC is tied to a non-monotonic dependence of bipolar current gain on VG that reduces drain-source current through the QW. These devices establish the feasibility of exploiting quantum transport to transform the performance horizons of Si devices fabricated in an industrially scalable manner.
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    Theoretical Simulation of Negative Differential Transconductance in Lateral Quantum Well nMOS Devices
    (American Institute of Physics Inc, 2017-01-23) Vyas, P. B.; Naquin, C.; Edwards, H.; Lee, Mark; Vandenberghe, W. G.; Fischetti, Massimo V.; 0000-0001-5926-0200 (Fischetti, MV); 21146635654041982414 (Vandenberghe, WG); Vyas, P. B.; Lee, Mark; Vandenberghe, William G.; Fischetti, Massimo V.
    We present a theoretical study of the negative differential transconductance (NDT) recently observed in the lateral-quantum-well Si n-channel field-effect transistors J. Appl. Phys. 118, 124505 (2015)]. In these devices, p⁺ doping extensions are introduced at the source-channel and drain-channel junctions, thus creating two potential barriers that define the quantum well across whose quasi-bound states resonant/sequential tunneling may occur. Our study, based on the quantum transmitting boundary method, predicts the presence of a sharp NDT in devices with a nominal gate length of 10-to-20 nm at low temperatures (~10 K). At higher temperatures, the NDT weakens and disappears altogether as a result of increasing thermionic emission over the p⁺ potential barriers. In larger devices (with a gate length of 30 nm or longer), the NDT cannot be observed because of the low transmission probability and small energetic spacing (smaller than k_{B}T) of the quasi-bound states in the quantum well. We speculate that the inability of the model to predict the NDT observed in 40 nm gate-length devices may be due to an insufficiently accurate knowledge of the actual doping profiles. On the other hand, our study shows that NDT suitable for novel logic applications may be obtained at room temperature in devices of the current or near-future generation (sub-10 nm node), provided an optimal design can be found that minimizes the thermionic emission (requiring high p⁺ potential-barriers) and punch-through (that meets the opposite requirement of potential-barriers low enough to favor the tunneling current).

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