Makris, Yiorgos

Permanent URI for this collectionhttps://hdl.handle.net/10735.1/7777

Yiorgos Makris is a Professor of Electrical and Computer Engineering. He leads the Trusted and RELiable Architectures (TRELA) Research Laboratory, the Safety, Security and Health Care Thrust of the Texas Analog Center of Excellence (TxACE), and the UT Dallas site of the NSF Industry University Cooperative Research Center (IUCRC) on Hardware and Embedded System Security and Trust (CHEST). His research interests include:

  • Hardware Security and Trustworthiness
  • Applications of Machine Learning in Robust Design & Test of Analog/RF ICs
  • Workload-Cognizant Reliable Design of Modern Microprocessors
  • Smart Observer Modules for Reliable Analog Circuits
  • Test and Reliability Solutions for Asynchronous Circuits
  • Test and Reliability Solutions for Digital Circuits

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    Wafer-Level Adaptive Vₘᵢₙ Calibration Seed Forecasting
    (Institute of Electrical and Electronics Engineers Inc., 2019-03-25) Xanthopoulos, Constantinos; Neethirajan, Deepika; Boddikurapati, S.; Nahar, A.; Makris, Yiorgos; Xanthopoulos, Constantinos; Neethirajan, Deepika; Makris, Yiorgos
    To combat the effects of process variation in modern, high-performance integrated Circuits (ICs), various post-manufacturing calibrations are typically performed. These calibrations aim to bring each device within its specification limits and ensure that it abides by current technology standards. Moreover, with the increasing popularity of mobile devices that usually depend on finite energy sources, power consumption has been introduced as an additional constraint. As a result, post-silicon calibration is often performed to identify the optimal operating voltage (Vₘᵢₙ) of a given Integrated Circuit. This calibration is time-consuming, as it requires the device to be tested in a wide range of voltage inputs across a large number of tests. In this work, we propose a machine learning-based methodology for reducing the cost of performing the Vₘᵢₙ calibration search, by identifying the optimal wafer-level search parameters. The effectiveness of the proposed methodology is demonstrated on an industrial dataset. © 2019 EDAA.

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