Gohil, Ghanshyamsinh V.

Permanent URI for this collectionhttps://hdl.handle.net/10735.1/6563

Ghanshyamsinh Gohil is Assistant Professor of Electrical and Computer Engineering and head of the Power Electronics Lab. His research interests include:

  • Power electronics
  • Wide-band gap devices
  • Micro-grid
  • High frequency power conversion
  • Medium voltage power conversion
  • Design optimization
  • Pulsewidth modulation
  • Inductive power components

ORCID page


Recent Submissions

Now showing 1 - 3 of 3
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    Benchmarking and Qualification of Gate Drivers for Medium Voltage (MV) Operation Using 10 Kv Silicon Carbide (SiC) Mosfets
    (Institute of Electrical and Electronics Engineers Inc., 2019-03) Anurag, A.; Acharya, S.; Gohil, Ghanshyamsinh; Bhattacharya, S.; 0000-0001-7875-4759 (Gohil, GV); Gohil, Ghanshyamsinh
    Emergence of reliable medium voltage (MV) silicon carbide (SiC) devices, has made it possible to use these for MV applications, including grid interconnections, and medium voltage drives system. In a converter structure, the isolated power supplies of the gate drivers for these MV devices experience a peak stress up to 15 kV and a very high dv/dt (up to 100 kV/μs). Exposing the gate driver to such harsh conditions leads to various challenges in providing the required insulation, and maintaining the signal fidelity (due to common mode (CM) currents across the parasitic capacitance of the transformer). The failure of gate drivers at a converter level can lead to destructive damage to the converter. This calls for a methodology to design, test and qualify the gate drivers before implementing them in the field for long-term operation. This paper provides a detailed design methodology and analysis to qualify the gate drivers for a long-term operation. The analysis and design-phase ensures reliable operation of the gate driver, and the testing and qualifying phase ensures long-term operation of the gate driver. The experimental test setup has been built and test results have been provided based on a gate driver designed for 10 kV SiC MOSFETs. © 2019 IEEE.
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    Static and Dynamic Characterization of a 3.3 kV, 45 A 4H-SiC MOSFET
    (Trans Tech Publications Ltd) Anurag, A.; Gohil, Ghanshyamsinh; Acharya, S.; Han, K.; Vechalapu, K.; Baliga, B. J.; Bhattacharya, S.; Van brunt, E.; Sabri, S.; Hull, B.; Grider, D.; Gohil, Ghanshyamsinh
    Wide bandgap materials such as Silicon Carbide (SiC) has enabled the use of medium voltage unipolar devices like Metal-Oxide Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs), which can switch at much higher frequencies as compared to their silicon counterparts. It is therefore imperative to evaluate the performance of these medium voltage devices. In this paper, the static characterization and the switching performance of the new single die 3.3 kV, 45 A 4H-SiC MOSFET developed by Cree Inc are presented. The switching performance is measured through the conventional Double Pulse Test (DPT). Testing is done at a dc-link voltage of 1.5 kV for different values of current, and gate resistances. ©2018 Trans Tech Publications, Switzerland.
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    Design Considerations and Development of an Innovative Gate Driver for Medium Voltage Power Devices with High dv/dt
    (Institute of Electrical and Electronics Engineers Inc.) Anurag, A.; Acharya, S.; Prabowo, Y.; Gohil, Ghanshyamsinh V.; Bhattacharya, S.; 0000-0001-7875-4759 (Gohil, GV); Gohil, Ghanshyamsinh V.
    Medium Voltage (MV) Silicon Carbide (SiC) devices have opened up new areas of applications which were previously dominated by silicon based IGBTs. From the perspective of a power converter design, the development of MV SiC devices eliminates the need for series connected architectures, control of multilevel converter topologies which are necessary for MV applications, and the inherent reliability issues associated with it. However, when SiC devices are used in these applications, they are exposed to a high peak stress (5 kV to 10 kV) and a very high dv/dt (10 kV/ μs to 100 kV/ μs). Using these devices calls for a gate driver with dc-dc isolation stage which has ultra-low coupling capacitance in addition to be able to withstand the high isolation voltage. This paper presents a new MV gate driver design to address these issues while maintaining a minimal footprint for the gate driver. A medium voltage isolation transformer is designed with a low inter-winding capacitance, while maintaining the clearance, creepage, as well as insulation standards. A dc isolation test has been performed to validate the integrity of the insulating material. The key features include low input common mode current, and a short circuit protection scheme specifically designed for 10 kV SiC MOSFETs. The performance of the gate driver is evaluated using double pulse tests and continuous tests. Experimental results validate the advantages of the gate driver and its application for medium voltage SiC devices exhibiting very high dv/dt. The proposed gate driver concept is aimed at providing an efficient and reliable method to drive MV SiC devices.

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