The Sequence Detection Algorithm and Error-Tolerant ADC for High-Precision Detection in High-Energy Physics Experiment




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The fast-moving digital-driven very large scale integration (VLSI) development enables the implementation of complexed and sophisticated digital signal processing (DSP) algorithm and stimulating the generic structure of analog-to-digital converter (ADC) plus DSP structures applied in many application scenarios. Benefits from this general trend, the frontend electronics in the readout system and the backend DSP algorithms for the next phase ATLAS experiment at large hadron collider (LHC) is under evaluation and design for high-precision detection. This research focused on the backend DSP algorithms and the related ADC design, which is required to be error-tolerant to convey high-performance analog-to-digital (A/D) conversion in the radiation environment.

Based on the seminal work of liner optimal filter (LOF) by W. Cleland et al., this research devised a sequence detection algorithm with the extended LOF and decision feedback equalization (DFE) technique to remove the increasing pileup effects in the high-luminosity environment. Various Monte Carlo simulations validate the effectiveness of this proposed algorithm – neither missing detection nor false alarm is observed for medium- to high-energy particles. The proposed algorithm maintains the same detection efficiency in the upgrade phase as that of the LOF in the current phase, demonstrating its superior performance to that of the LOF for high-luminosity detection.

As required by the proposed algorithm, high-resolution and throughput ADCs are in demand to deliver large dynamic range, high SNR and fast sample rate. The operation environment also requires the ADC to be radiation-tolerant. A two-step split successive-approximation register (SAR) ADC is proposed and implemented in 65-nm CMOS to fulfill the above requirements. The prototype measures 78.5 dB peak SNDR and over 100 dB peak SFNR at 35 MS/s sample rate and >70 dB SNDR and >88 dB SFDR up to Nyquist frequency at 75 MS/s sample rate. Besides, multiple new error detection techniques are developed and implemented. Combining with the redundancies allocated in each circuit hierarchy, the prototype demonstrated 100% error correction rate in the single event effect (SEE) test with proton beam. Less than 1 dB maximum degradation of SNDR and SFDR in the total ionizing dose (TID) with X-ray proves its long-term radiation-tolerant feature. The prototype consumes 22.2 mW at 40 MS/s and 24.9 mW at 75 MS/s sample rate.



Integrated circuits—Very large scale integration, Signal processing—Digital techniques, Successive approximation analog-to-digital converters, Radiation tolerance, Metastasis


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