An Efficient Bayesian Yield Estimation Method for High Dimensional and High Sigma SRAM Circuits



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Institute of Electrical and Electronics Engineers Inc.


With increasing dimension of variation space and computational intensive circuit simulation, accurate and fast yield estimation of realistic SRAM chip remains a significant and complicated challenge. In this paper, du Experiment results show that the proposed method has an almost constant time complexity as the dimension increases, and gains 6x speedup over the state-of-the-art method in the 485D cases.


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Computer-aided design, Timing circuits, Bayesian statistical decision theory, SRAM (Static random access memory), Integrated circuits--Computer simulation, Electronic circuits--Computer simulation

National Major Science and Technology Special Project of China (2017ZX01028101-003); National Natural Science Foundation of China (NSFC) research projects 61674042, 61574044, 61574046, 61774045, and 61628402; NSF Grant 1115564.


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