An Efficient Bayesian Yield Estimation Method for High Dimensional and High Sigma SRAM Circuits
Date
Authors
ORCID
Journal Title
Journal ISSN
Volume Title
Publisher
Institute of Electrical and Electronics Engineers Inc.
item.page.doi
Abstract
With increasing dimension of variation space and computational intensive circuit simulation, accurate and fast yield estimation of realistic SRAM chip remains a significant and complicated challenge. In this paper, du Experiment results show that the proposed method has an almost constant time complexity as the dimension increases, and gains 6x speedup over the state-of-the-art method in the 485D cases.
Description
Full text access from Treasures at UT Dallas is restricted to current UTD affiliates (use the provided Link to Article). Non UTD affiliates will find the web address for this item by clicking the "Show full item record" link, copying the "dc.relation.uri" metadata and pasting it into a browser.
Keywords
Computer-aided design, Timing circuits, Bayesian statistical decision theory, SRAM (Static random access memory), Integrated circuits--Computer simulation, Electronic circuits--Computer simulation
item.page.sponsorship
National Major Science and Technology Special Project of China (2017ZX01028101-003); National Natural Science Foundation of China (NSFC) research projects 61674042, 61574044, 61574046, 61774045, and 61628402; NSF Grant 1115564.
Rights
©2018 Association for Computing Machinery