Overhead Requirements for Stateful Memristor Logic

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dc.contributor.ORCID0000-0001-9847-4455 (Friedman, JS)
dc.contributor.authorHu, Xuan
dc.contributor.authorSchultis, Michael J.
dc.contributor.authorKramer, Matthew
dc.contributor.authorBagla, Archit
dc.contributor.authorShetty, Akshay
dc.contributor.authorFriedman, Joseph S.
dc.contributor.utdAuthorHu, Xuan
dc.contributor.utdAuthorSchultis, Michael J.
dc.contributor.utdAuthorKramer, Matthew
dc.contributor.utdAuthorBagla, Archit
dc.contributor.utdAuthorShetty, Akshay
dc.contributor.utdAuthorFriedman, Joseph S.
dc.date.accessioned2020-05-07T15:04:11Z
dc.date.available2020-05-07T15:04:11Z
dc.date.issued2019-01
dc.descriptionDue to copyright restrictions and/or publisher's policy full text access from Treasures at UT Dallas is limited to current UTD affiliates (use the provided Link to Article).
dc.description.abstractMemristors are being explored as a potential technology to replace CMOS for logic-in-memory systems that exploit the memristive non-volatility. Memristors are two-terminal, non-volatile device that exhibit a variable resistance that is dependent on the applied voltage history of the device, providing the capability to store and process information within the same structure. The ability of memristors to perform logic has been previously demonstrated, but previous analyses of memristor logic efficiency have not included the overhead CMOS circuitry that is required to control memristor logic operations. In this paper, the required overhead CMOS circuitry for implementing logic with memristors is evaluated for standard logic gates and a one-bit full adder to enable an analysis of the overall system efficiency. The results show that the number of CMOS devices in the overhead circuitry can be upwards of 50 times that of a conventional CMOS implementation, and that the power-delay product of the memristor logic with overhead circuitry is roughly one billion times greater than for conventional CMOS circuits. These results enable the conclusion that the overhead circuit requirements for stateful memristor logic threaten to negate any efficiency improvements that are achieved by the memristors themselves.
dc.description.departmentErik Jonsson School of Engineering and Computer Science
dc.identifier.bibliographicCitationHu, Xuan, Michael J. Schultis, Matthew Kramer, Archit Bagla, et al. 2019. "Overhead Requirements for Stateful Memristor Logic." IEEE Transactions on Circuits and Systems I: Regular Papers 66(1): 263-273, doi: 10.1109/TCSI.2018.2861463
dc.identifier.issn1549-8328
dc.identifier.issue1
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2018.2861463
dc.identifier.urihttps://hdl.handle.net/10735.1/8525
dc.identifier.volume66
dc.language.isoen
dc.publisherIEEE-Institute of Electrical Electronics Engineers Inc
dc.rights©2019 IEEE
dc.source.journalIEEE Transactions on Circuits and Systems I: Regular Papers
dc.subjectMemristors
dc.subjectTransistors
dc.subjectOverhead circuits
dc.titleOverhead Requirements for Stateful Memristor Logic
dc.type.genrearticle

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