Friedman, Joseph S.
Permanent URI for this collectionhttps://hdl.handle.net/10735.1/6783
Joseph Friedman is Assistant Professor of Electrical and Computer Engineering. He also serves as the Director of the NeuroSpinCompute Laboratory. His research objective is to "invent, design, and analyze novel logical and neuromorphic computing paradigms that exploit nanoscale phenomena to achieve greater capabilities than conventional CMOS architectures." His research projects have included:
- All-Carbon Spin Logic
- Magnetic Domain Wall Neuron
- Complementary Magnetic Tunnel Junction Logic (CMAT)
- Spin-Diode Logic
- Four-Gate FET Threshold Logic
- Stochastic Bayesian Inference
- Spin-Transfer Torque Logic with Ferromagnetic Nanowires
- Efficient Carbon Nanotube Logic Circuits
- Novel Techniques for Stateful Memristor Logic
- Skyrmion Logic
- Spintronic FPGA
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Item Overhead Requirements for Stateful Memristor Logic(IEEE-Institute of Electrical Electronics Engineers Inc, 2019-01) Hu, Xuan; Schultis, Michael J.; Kramer, Matthew; Bagla, Archit; Shetty, Akshay; Friedman, Joseph S.; 0000-0001-9847-4455 (Friedman, JS); Hu, Xuan; Schultis, Michael J.; Kramer, Matthew; Bagla, Archit; Shetty, Akshay; Friedman, Joseph S.Memristors are being explored as a potential technology to replace CMOS for logic-in-memory systems that exploit the memristive non-volatility. Memristors are two-terminal, non-volatile device that exhibit a variable resistance that is dependent on the applied voltage history of the device, providing the capability to store and process information within the same structure. The ability of memristors to perform logic has been previously demonstrated, but previous analyses of memristor logic efficiency have not included the overhead CMOS circuitry that is required to control memristor logic operations. In this paper, the required overhead CMOS circuitry for implementing logic with memristors is evaluated for standard logic gates and a one-bit full adder to enable an analysis of the overall system efficiency. The results show that the number of CMOS devices in the overhead circuitry can be upwards of 50 times that of a conventional CMOS implementation, and that the power-delay product of the memristor logic with overhead circuitry is roughly one billion times greater than for conventional CMOS circuits. These results enable the conclusion that the overhead circuit requirements for stateful memristor logic threaten to negate any efficiency improvements that are achieved by the memristors themselves.Item Spice-Only Model for Spin-Transfer Torque Domain Wall MTJ Logic(Institute of Electrical and Electronics Engineers Inc., 2019 IEEE) Hu, Xuan; Timm, Andrew; Brigner, Wesley H.; Incorvia, J. A. C.; Friedman, Joseph S.; 0000-0001-9847-4455 (Friedman, JS); 0000-0002-7337-6637 (Hu, X); Hu, Xuan; Timm, Andrew; Brigner, Wesley H.; Friedman, Joseph S.The spin-transfer torque domain wall (DW) magnetic tunnel junction (MTJ) enables spintronic logic circuits that can be directly cascaded without deleterious signal conversion circuitry and is one of the only spintronic devices for which cascading has been demonstrated experimentally. However, experimental progress has been impeded by a cumbersome modeling technique that requires a combination of micromagnetic and SPICE simulations. This paper, therefore, presents a SPICE-only device model that efficiently determines the DW motion resulting from spin accumulation and calculates the corresponding MTJ resistance. This model has been validated through comparison to the authoritative micromagnetic-based model, enabling reliable prediction of circuit behavior as a function of device parameters with a 10 000 × reduction in the simulation time. This model thus enables deeper device and circuit investigation, advancing the prospects for nonvolatile spintronic computing systems that overcome the von Neumann bottleneck. ©2019 IEEE.Item Graded-Anisotropy-Induced Magnetic Domain Wall Drift for an Artificial Spintronic Leaky Integrate-and-Fire Neuron(Institute of Electrical and Electronics Engineers Inc., 2019-03-11) Brigner, Wesley H.; Hu, Xuan; Hassan, Naimul; Bennett, C. H.; Incorvia, J. A. C.; Garcia-Sanchez, F.; Friedman, Joseph S.; 0000-0001-9847-4455 (Friedman, JS); 0000-0001-6202-3193 (Brigner, WH); 0000-0002-7337-6637 (Hu, X); Brigner, Wesley H.; Hu, Xuan; Hassan, Naimul; Friedman, Joseph S.Spintronic three-terminal magnetic-tunnel-junction (3T-MTJ) devices have gained considerable interest in the field of neuromorphic computing. Previously, these devices required external circuitry to implement the leaking functionality that leaky integrate-and-fire (LIF) neurons should display. However, the use of external circuitry results in decreased device efficiency. We previously demonstrated lateral inhibition with a 3T-MTJ neuron that intrinsically performs the leaking, integrating, and firing functions; however, it required the fabrication of a complex multilayer structure. In this paper, we introduce an anisotropy gradient to implement a single-layer intrinsically leaking 3T-MTJ LIF neuron without the use of any external circuitry. This provides the leaking functionality with no hardware cost and reduced fabrication complexity, which increases the device, circuit, system, and cost efficiency.Item Overhead Requirements for Stateful Memristor Logic(Institute of Electrical and Electronics Engineers Inc.) Hu, Xuan; Schultis, Michael J.; Kramer, Matthew; Bagla, Archit; Shetty, Akshay; Friedman, Joseph S.; 0000-0002-7337-6637 (Hu, X); 0000-0002-5893-9876 (Shetty, A); 0000-0001-9847-4455 (Friedman, JS); Hu, Xuan; Schultis, Michael J.; Kramer, Matthew; Bagla, Archit; Shetty, Akshay; Friedman, Joseph S.Memristors are being explored as a potential technology to replace CMOS for logic-in-memory systems that exploit the memristive non-volatility. Memristors are two-terminal, non-volatile device that exhibit a variable resistance that is dependent on the applied voltage history of the device, providing the capability to store and process information within the same structure. The ability of memristors to perform logic has been previously demonstrated, but previous analyses of memristor logic efficiency have not included the overhead CMOS circuitry that is required to control memristor logic operations. In this paper, the required overhead CMOS circuitry for implementing logic with memristors is evaluated for standard logic gates and a one-bit full adder to enable an analysis of the overall system efficiency. The results show that the number of CMOS devices in the overhead circuitry can be upwards of 50 times that of a conventional CMOS implementation, and that the power-delay product of the memristor logic with overhead circuitry is roughly one billion times greater than for conventional CMOS circuits. These results enable the conclusion that the overhead circuit requirements for stateful memristor logic threaten to negate any efficiency improvements that are achieved by the memristors themselves.