Hardware Implementation of Real-Time Beat Detection and Classification Algorithm for Automated ECG Analysis

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dc.contributor.advisorTamil, Lakshman S.
dc.creatorGhosh, Ria
dc.date.accessioned2018-10-08T19:16:28Z
dc.date.available2018-10-08T19:16:28Z
dc.date.created2018-08
dc.date.issued2018-08
dc.date.submittedAugust 2018
dc.date.updated2018-10-08T19:16:28Z
dc.description.abstractThe epidemics of diabetes and obesity, along with unhealthy and stressful lifestyles, have highly contributed to the increased number of patients with heart failure in recent times. As the saying goes, “Prevention is better than cure”, detecting heart abnormalities accurately in initial stages can save patients from severe consequences and expensive surgeries. Hence, in the past few years there has been extensive research in beat detection and real-time cardiac monitoring to determine algorithms that can detect heart beat location and analyze whether the distance between two beats are normal or not. Such a regular check on the health of the heart using a device that could give real-time cardiac monitoring outside the hospital helps to ensure early diagnosis of any kind of abnormality that the cardiac system of an individual might be facing or is prone to face in the near future. Various QRS complex detecting algorithms have been implemented into smart watches and fitness trackers, which has led to the commercialization of various wearable heart beat monitoring devices that have been effective to quite an extent. However, various factors like unwanted noise and inconsistency in differentiating beat locations, may reduce the accuracy of such devices. Hence, it is necessary to ensure that any algorithm maintains accurate precision during both software and hardware testing. Therefore, this thesis aims towards analyzing and confirming the accuracy of the hardware implementation of a Real-time QRS complex detector and Heart Beat classifier using an algorithm based on the modified Pan Tompkins algorithm, which sets a threshold for detecting the peak locations and then classifies them as normal or ventricular. The algorithm, which is a single-lead, first derivative based heart-beat detector and classifier, has been coded in MATLAB. Then using MATLAB’s HDL Coder and System Generator applications, it was converted to VHDL. VHDL is the hardware descriptive language that can communicate with our FPGA board in Xilinx ISE 14.7. All analysis and conclusions have been verified using the SPARTAN-6 FPGA board specifications.
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/10735.1/6187
dc.language.isoen
dc.rights©2018 The Author. Digital access to this material is made possible by the Eugene McDermott Library. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
dc.subjectArrhythmia—Diagnosis
dc.subjectHeart beat
dc.subjectHeart—Ventricles
dc.subjectField programmable gate arrays
dc.subjectVHDL (Computer hardware description language)
dc.subjectComputer algorithms
dc.titleHardware Implementation of Real-Time Beat Detection and Classification Algorithm for Automated ECG Analysis
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentComputer Engineering
thesis.degree.grantorThe University of Texas at Dallas
thesis.degree.levelMasters
thesis.degree.nameMS

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