Wafer-Level Adaptive Vₘᵢₙ Calibration Seed Forecasting

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dc.contributor.authorXanthopoulos, Constantinos
dc.contributor.authorNeethirajan, Deepika
dc.contributor.authorBoddikurapati, S.
dc.contributor.authorNahar, A.
dc.contributor.authorMakris, Yiorgos
dc.contributor.utdAuthorXanthopoulos, Constantinos
dc.contributor.utdAuthorNeethirajan, Deepika
dc.contributor.utdAuthorMakris, Yiorgos
dc.date.accessioned2020-04-02T20:54:42Z
dc.date.available2020-04-02T20:54:42Z
dc.date.issued2019-03-25
dc.descriptionDue to copyright restrictions and/or publisher's policy full text access from Treasures at UT Dallas is limited to current UTD affiliates (use the provided Link to Article).
dc.description.abstractTo combat the effects of process variation in modern, high-performance integrated Circuits (ICs), various post-manufacturing calibrations are typically performed. These calibrations aim to bring each device within its specification limits and ensure that it abides by current technology standards. Moreover, with the increasing popularity of mobile devices that usually depend on finite energy sources, power consumption has been introduced as an additional constraint. As a result, post-silicon calibration is often performed to identify the optimal operating voltage (Vₘᵢₙ) of a given Integrated Circuit. This calibration is time-consuming, as it requires the device to be tested in a wide range of voltage inputs across a large number of tests. In this work, we propose a machine learning-based methodology for reducing the cost of performing the Vₘᵢₙ calibration search, by identifying the optimal wafer-level search parameters. The effectiveness of the proposed methodology is demonstrated on an industrial dataset. © 2019 EDAA.
dc.description.departmentErik Jonsson School of Engineering and Computer Science
dc.description.sponsorshipSemiconductor Research Corporation (SRC) task 2712.031
dc.identifier.bibliographicCitationXanthopoulos, C., D. Neethirajan, S. Boddikurapati, A. Nahar, et al. 2019. "Wafer-Level Adaptive Vₘᵢₙ Calibration Seed Forecasting." Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition: 1673-1678, doi: 10.23919/DATE.2019.8715082
dc.identifier.isbn9783981926323
dc.identifier.urihttp://dx.doi.org/10.23919/DATE.2019.8715082
dc.identifier.urihttps://hdl.handle.net/10735.1/7778
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.relation.isPartOfProceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition
dc.rights©2019 EDAA
dc.subjectComputer adaptive testing
dc.subjectSilicon--Calibration
dc.subjectCalibration
dc.subjectCost control
dc.subjectIntegrated circuits
dc.subjectInstructional systems
dc.subjectWafers, Silicon
dc.subjectElectronic circuits--Testing--Equipment and supplies
dc.titleWafer-Level Adaptive Vₘᵢₙ Calibration Seed Forecasting
dc.type.genrearticle

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