IC Laser Trimming Speed-up Through Wafer-Level Spatial Correlation Modeling
| dc.contributor.advisor | Makris, Yiorgos | |
| dc.creator | Xanthopoulos, Konstantinos | |
| dc.date.accessioned | 2020-03-04T18:14:08Z | |
| dc.date.available | 2020-03-04T18:14:08Z | |
| dc.date.created | 2019-12 | |
| dc.date.issued | 2019-12 | |
| dc.date.submitted | December 2019 | |
| dc.date.updated | 2020-03-04T18:14:09Z | |
| dc.description.abstract | Laser trimming is used extensively to ensure accurate values of on-chip precision resistors in the presence of process variations. Such laser resistor trimming is slow and expensive, typically performed in a closed-loop, where the laser is iteratively fired and some circuit parameter (i.e. current) is monitored until a target condition is satisfied. Toward reducing this cost, we introduce a novel methodology for predicting the laser trim length, thereby eliminating the closed-loop control and speeding up the process. Predictions are obtained from wafer-level spatial correlation models, learned from a sparse sample of die on which traditional trimming is performed. Effectiveness is demonstrated on an actual wafer of lasertrimmed ICs. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | https://hdl.handle.net/10735.1/7336 | |
| dc.language.iso | en | |
| dc.rights | ©2019 Konstantinos Xanthopoulos. All Rights Reserved. | |
| dc.subject | Laser beam cutting | |
| dc.subject | Computer adaptive testing | |
| dc.subject | Cost control | |
| dc.title | IC Laser Trimming Speed-up Through Wafer-Level Spatial Correlation Modeling | |
| dc.type | Thesis | |
| dc.type.material | text | |
| thesis.degree.department | Computer Engineering | |
| thesis.degree.grantor | The University of Texas at Dallas | |
| thesis.degree.level | Masters | |
| thesis.degree.name | MS |
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