Theoretical Simulation of Negative Differential Transconductance in Lateral Quantum Well nMOS Devices

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dc.contributor.ORCID0000-0001-5926-0200 (Fischetti, MV)en_US
dc.contributor.VIAF21146635654041982414 (Vandenberghe, WG)en_US
dc.contributor.authorVyas, P. B.en_US
dc.contributor.authorNaquin, C.en_US
dc.contributor.authorEdwards, H.en_US
dc.contributor.authorLee, Marken_US
dc.contributor.authorVandenberghe, W. G.en_US
dc.contributor.authorFischetti, Massimo V.en_US
dc.contributor.utdAuthorVyas, P. B.en_US
dc.contributor.utdAuthorLee, Marken_US
dc.contributor.utdAuthorVandenberghe, William G.en_US
dc.contributor.utdAuthorFischetti, Massimo V.en_US
dc.date.accessioned2018-09-24T15:06:47Z
dc.date.available2018-09-24T15:06:47Z
dc.date.created2017-01-23
dc.date.issued2017-01-23en_US
dc.description.abstractWe present a theoretical study of the negative differential transconductance (NDT) recently observed in the lateral-quantum-well Si n-channel field-effect transistors J. Appl. Phys. 118, 124505 (2015)]. In these devices, p⁺ doping extensions are introduced at the source-channel and drain-channel junctions, thus creating two potential barriers that define the quantum well across whose quasi-bound states resonant/sequential tunneling may occur. Our study, based on the quantum transmitting boundary method, predicts the presence of a sharp NDT in devices with a nominal gate length of 10-to-20 nm at low temperatures (~10 K). At higher temperatures, the NDT weakens and disappears altogether as a result of increasing thermionic emission over the p⁺ potential barriers. In larger devices (with a gate length of 30 nm or longer), the NDT cannot be observed because of the low transmission probability and small energetic spacing (smaller than k_{B}T) of the quasi-bound states in the quantum well. We speculate that the inability of the model to predict the NDT observed in 40 nm gate-length devices may be due to an insufficiently accurate knowledge of the actual doping profiles. On the other hand, our study shows that NDT suitable for novel logic applications may be obtained at room temperature in devices of the current or near-future generation (sub-10 nm node), provided an optimal design can be found that minimizes the thermionic emission (requiring high p⁺ potential-barriers) and punch-through (that meets the opposite requirement of potential-barriers low enough to favor the tunneling current).en_US
dc.description.departmentSchool of Natural Sciences and Mathematicsen_US
dc.description.sponsorshipNational Science Foundation under Grant No. ECCS-1403421en_US
dc.identifier.bibliographicCitationVyas, P. B., C. Naquin, H. Edwards, M. Lee, et al. 2017. "Theoretical simulation of negative differential transconductance in lateral quantum well nMOS devices." Journal of Applied Physics 121(4), doi:10.1063/1.4974469en_US
dc.identifier.issn0021-8979en_US
dc.identifier.issue4en_US
dc.identifier.urihttp://hdl.handle.net/10735.1/6100
dc.identifier.volume121en_US
dc.language.isoenen_US
dc.publisherAmerican Institute of Physics Incen_US
dc.relation.urihttp://dx.doi.org/10.1063/1.4974469
dc.rights©2017 American Institute of Physics.en_US
dc.sourceJournal of Applied Physics
dc.subjectField-effect transistorsen_US
dc.subjectQuantum theoryen_US
dc.subjectElectron tubes—Thermionic emissionen_US
dc.subjectSimulation methodsen_US
dc.subjectSemiconductorsen_US
dc.subjectQuantum wellsen_US
dc.titleTheoretical Simulation of Negative Differential Transconductance in Lateral Quantum Well nMOS Devicesen_US
dc.type.genrearticleen_US

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Fischetti, Massimo V.
Lee, Mark
Vandenberghe, William G.