Design and Optimization of Behavioral Application Specific Processors

Most modern Integrated Circuits (ICs) are heterogeneous System-on-Chip (SoC) that include multiple embedded processors, on-chip memories, different types of serial interfaces and a growing number of dedicated hardware accelerators. The embedded processors are customized to the application domain for optimal performance and energy efficiency. This further increases the complexity of designing, optimizing and verifying the entire system. To address this, in this thesis I have proposed different automatic design flows for the efficient design and optimization of application specific processors (ASIPs) using High-Level Synthesis (HLS). HLS is a promising approach that raises the level of abstraction of VLSI design from the RT level to the behavioral level. These flows range from building near on-chip memory processing systems to optimized embedded processors with tightly integrated hardware (HW) accelerators. In all cases, the proposed systems lead to significant area, performance and/or power improvements by leveraging some of the main advantages of HLS like being able to efficiently share HW resources.