Flexible Partial Reconfiguration Based Design Architecture for Dataflow Computation

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dc.contributor.advisorSchaefer, Benjamin Carrion
dc.creatorShah, Mihir
dc.date.accessioned2018-08-03T17:20:42Z
dc.date.available2018-08-03T17:20:42Z
dc.date.created2018-05
dc.date.issued2018-05
dc.date.submittedMay 2018
dc.date.updated2018-08-03T17:20:44Z
dc.description.abstractIn this thesis research we proposed a generic semi-automatic partial reconfiguration based design methodology which takes inputs in the form of behavioral description files using C/C++/SystemC for a dataflow process and outputs partial binaries to deploy on the SoC FPGA. This methodology is coupled with a novel static design architectural framework utilizing internal block ram memory to store intermediate results. In order to prove the efficacy of the proposed methodology and architecture in terms of area and timing, we have implemented JPEG Encoder from S2CBench v.2.0 spatially and then with partial reconfiguration design methodologies. The proposed design method abbreviated as PRBRAM where internal FPGA on-chip memory is used to store intermediate results when time multiplexing kernels and PRDDR is a partial reconfiguration based design method utilizing external off-chip DDR memory. The reconfiguration time is a critical parameter determining the performance of DPR designs. Reconfiguration time depends on the area of Reconfigurable Partition (RP) and the generated partial bitstream. Thus, we study and prove experimentally considering equal area of RP for both PRBRAM & PRDDR, that the proposed former method is runtime and latency efficient compared to the latter. We also examine and study the effects of variations on reconfigurable partition area on running time, considering different number of reconfigurations required for the application on the proposed architecture PRBRAM. We prove that the implementation with the proposed Architecture PRBRAM is area efficient compared to spatial implementation with LUT area savings upto 21.20 % and FF area savings up to 30.41 % for 1598.896 KB as partial bitstream size. These %’s are including the additional resources utilized by proposed static architecture. We also have seen an improvement in average hardware running of 0.529363s against PRDDR.
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/10735.1/5919
dc.language.isoen
dc.rights©2018 The Author. Digital access to this material is made possible by the Eugene McDermott Library. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
dc.subjectAdaptive computing systems
dc.subjectData flow computing
dc.subjectJPEG (Image coding standard)
dc.titleFlexible Partial Reconfiguration Based Design Architecture for Dataflow Computation
dc.typeThesis
dc.type.materialtext
thesis.degree.departmentElectrical Engineering
thesis.degree.grantorThe University of Texas at Dallas
thesis.degree.levelMasters
thesis.degree.nameMSEE

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