Low Noise Integrated Circuits and Systems Using Nano-Scale MOSFETs and Intelligent Post-Fabrication Selection

dc.contributor.advisorO, Kenneth K.
dc.contributor.advisorVenkatesan, Subbarayan
dc.contributor.committeeMemberHenderson, Rashaunda
dc.contributor.committeeMemberMa, Donsheng Brian
dc.contributor.committeeMemberMakris, Yiorgos
dc.creatorYelleswarapu, Venkata Pavan Kumar
dc.date.issuedDecember 2021
dc.date.submittedDecember 2021
dc.description.abstractRecent advances in integrated radio design have enabled many applications such as wearable healthcare, 5G communication, and beyond 5G or 6G applications for ultra-high data rate communications, high-resolution imaging, sensing, and spectroscopy. All these applications require low noise radio transceivers for achieving high performance. For example, applications requiring high data rate and higher order modulation schemes need to achieve high signal to noise ratio (SNR) and therefore a low noise figure to maintain a low bit-error rate (BER). In addition, noise phenomena like jitter and phase noise can impact the critical parameters like maximum achievable data rate and energy efficiency. This research aims to improve the noise performance of integrated circuits and systems through intelligent post-fabrication selection of an array of nanoscale transistors sized near the minimum in CMOS processes. A phase noise reduction technique in LC Voltage Controlled Oscillators (VCO’s) is demonstrated by post-fabrication selection of a subset of an array of near minimum-size cross-coupled transistor pairs with reduced low frequency noise and thermal noise. The technique reduces the phase noise by taking advantage of the fact that when transistor dimensions are reduced, the low frequency noise and thermal noise vary significantly. Applying an intelligent post-fabrication selection process using a genetic algorithm, the lowest phase noise of -122 dBc/Hz, -127 dBc/Hz, -137.5 dBc/Hz at 600-kHz, 1-MHz, and 3-MHz offsets, respectively from a 3.8-GHz carrier has been measured. The VCO prototype was fabricated in a 65-nm CMOS process and dissipates 7 mW of DC power. The maximum figure of merit (FoM) including phase noise, carrier frequency and power consumption is 191 dBc/Hz and the figure of merit including the VCO core area, FoMA is 207 dBc/Hz. A technique is demonstrated to reduce both the in-band and out-of-band phase noise of a 4-GHz Integer-N PLL by employing an array of individually selectable cross-coupled pairs formed using near minimum-size transistors in an LC VCO and intelligent post-fabrication selection. By reducing both the in-band and out-of-band phase noise, the overall integrated phase jitter in a frequency synthesizer can be minimized. Applying an intelligent post-fabrication selection process, the lowest phase noise of -72 dBc/Hz at 30-kHz offset, -106 dBc/Hz at 300-kHz offset, -121.8 dBc/Hz at 1-MHz offset, and -132.5 dBc/Hz at 3-MHz offset, respectively from a 4.01-GHz locked carrier has been measured. The integrated rms jitter from 100-kHz to 100-MHz offsets is 440 fs. A mixer-first downconverter employing an array of passive mixers formed using near minimumsize transistors and intelligent post-fabrication selection achieves a double sideband noise figure of 4.2 dB at RF of 6 GHz, which is the lowest at 6 GHz for CMOS mixer-first downconverters. The downconverter is fabricated in 65-nm CMOS and demonstrates out-of-band IIP3 and IIP2 of 25 dBm and 65 dBm, respectively at 80-MHz IF, while dissipating 11.5 mW. Post-fabrication selection is performed by a genetic algorithm which takes ~17 generations to converge to the combinations exhibiting the lowest noise.
dc.subjectEngineering, Electronics and Electrical
dc.titleLow Noise Integrated Circuits and Systems Using Nano-Scale MOSFETs and Intelligent Post-Fabrication Selection
thesis.degree.collegeSchool of Engineering and Computer Science
thesis.degree.departmentElectrical Engineering
thesis.degree.grantorThe University of Texas at Dallas


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