Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network




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Institute of Electrical and Electronics Engineers Inc.


Bayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. In the traditional Gaussian process regression model, the kernel functions are defined explicitly. The computational complexity of training is O(N³), and the computation complexity of prediction is O(N²), where N is the number of training data. Gaussian process model can also be derived from a weight space view, where the original data are mapped to feature space, and the kernel function is defined as the inner product of nonlinear features. In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. We use deep neural network to extract good feature representations, and then define Gaussian process using the extracted features. Model averaging method is applied to improve the quality of uncertainty prediction. Compared to Gaussian process model with explicitly defined kernel functions, the neural-network-based Gaussian process model can automatically learn a kernel function from data, which makes it possible to provide more accurate predictions and thus accelerate the follow-up optimization procedure. Also, the neural-network-based model has O(N) training time and constant prediction time. The efficiency of the proposed method has been verified by two real-world analog circuits. © 2019 EDAA.


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Electronic analog computers—Circuits, Bayesian statistical decision theory, Gaussian processes, Neural networks (Computer science), Analog circuits, Forecasting, Random noise theory (electronic), Regression analysis, Timing circuits, Gaussian processes--Models

National Major Science and Technology Special Project of China (2017ZX01028101-003); National Natural Science Foundation of China (NSFC) research projects 61822402, 61574046, 61774045, 61674042 61574044, 61628402, and 61474026


©2019 EDAA