Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network

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dc.contributor.authorZhang, S.
dc.contributor.authorLyu, W.
dc.contributor.authorYang, F.
dc.contributor.authorYan, C.
dc.contributor.authorZhou, Dian
dc.contributor.authorZeng, X.
dc.contributor.utdAuthorZhou, Dian
dc.date.accessioned2020-04-06T23:18:52Z
dc.date.available2020-04-06T23:18:52Z
dc.date.issued2019-03-25
dc.descriptionDue to copyright restrictions and/or publisher's policy full text access from Treasures at UT Dallas is limited to current UTD affiliates (use the provided Link to Article).
dc.description.abstractBayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. In the traditional Gaussian process regression model, the kernel functions are defined explicitly. The computational complexity of training is O(N³), and the computation complexity of prediction is O(N²), where N is the number of training data. Gaussian process model can also be derived from a weight space view, where the original data are mapped to feature space, and the kernel function is defined as the inner product of nonlinear features. In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. We use deep neural network to extract good feature representations, and then define Gaussian process using the extracted features. Model averaging method is applied to improve the quality of uncertainty prediction. Compared to Gaussian process model with explicitly defined kernel functions, the neural-network-based Gaussian process model can automatically learn a kernel function from data, which makes it possible to provide more accurate predictions and thus accelerate the follow-up optimization procedure. Also, the neural-network-based model has O(N) training time and constant prediction time. The efficiency of the proposed method has been verified by two real-world analog circuits. © 2019 EDAA.
dc.description.departmentErik Jonsson School of Engineering and Computer Science
dc.description.sponsorshipNational Major Science and Technology Special Project of China (2017ZX01028101-003); National Natural Science Foundation of China (NSFC) research projects 61822402, 61574046, 61774045, 61674042 61574044, 61628402, and 61474026
dc.identifier.bibliographicCitationZhang, S., W. Lyu, F. Yang, C. Yan, et al. 2019. "Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network." Design, Automation and Test in Europe Conference and Exhibition, 2019: 1463-1468, doi: 10.23919/DATE.2019.8714788
dc.identifier.isbn9783981926323
dc.identifier.urihttp://dx.doi.org/10.23919/DATE.2019.8714788
dc.identifier.urihttps://hdl.handle.net/10735.1/7850
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.rights©2019 EDAA
dc.source.journalDesign, Automation and Test in Europe Conference and Exhibition, 2019
dc.subjectElectronic analog computers—Circuits
dc.subjectBayesian statistical decision theory
dc.subjectGaussian processes
dc.subjectNeural networks (Computer science)
dc.subjectAnalog circuits
dc.subjectForecasting
dc.subjectRandom noise theory (electronic)
dc.subjectRegression analysis
dc.subjectTiming circuits
dc.subjectGaussian processes--Models
dc.titleBayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network
dc.type.genrearticle

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