Browsing by Author "Zeng, X."
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Item A General Graph Based Pessimism Reduction Framework For Design Optimization Of Timing Closure(ACM) Peng, F.; Yan, C.; Feng, C.; Zheng, J.; Wang, S. -G; Zhou, Dian; Zeng, X.; Zhou, DianIn this paper, we develop a general pessimism reduction framework for design optimization of timing closure. Although the modified graph based timing analysis (mGBA) slack model can be readily formulated into a quadratic programming problem with constraints, the realistic difficulty is the size of the problem. A critical path selection scheme, a uniform sampling method with the sparse characteristics of the optimal solution, and a stochastic conjugate gradient method are proposed to accelerate the optimization solver. This modified GBA is embedded into design optimization of timing closure. Experimental results show that the proposed solver can achieve 13.82x speedup than gradient descent method with similar accuracy. With mGBA, the optimization of timing closure can achieve a better performance on area, leakage power, buffer counts.Item An Improved Domain Decomposition Method for Drop Impact Reliability Analysis of 3D ICs(Institute of Electrical and Electronics Engineers Inc.) Zhou, H.; Zhu, H.; Cui, T.; Pan, D. Z.; Zhou, D.; Zeng, X.Drop test is usually adopted in the integrated circuit (IC) testing to estimate the shock resistance capability of IC packaging. Generally, it is very time consuming for the drop test simulation, therefore, the fast numerical approach is generally needed to reduce the computational cost. In this paper, we propose an efficient drop-test simulator for through-siliconvia (TSV) based three-dimensional integrated circuit (3D IC) to simulate its mechanical behaviors under drop impact. The proposed simulator is based on the idea of domain decomposition (DD) to improve the condition number of the coefficient matrix of the solver. We further develop two efficient numerical techniques in the simulator to improve its efficiency. First, a second order formulation is proposed for the initial solution selection in preconditioned conjugate gradient (PCG) solver, which can efficiently reduce the number of PCG iterations at each time point during simulation. And second, an equivalent structureembedded model is proposed and applied in the first Schwarz iteration to efficiently reduce the number of Schwarz iterations in DD method. Numerical experiments show that the proposed drop-test simulator can achieve 7.03× speedup in comparison with the conventional FEM-based solver. It is demonstrated in the paper in the paper through several examples with multi chip layers, of which each chip layer consists of an 8 × 8 TSV array, that the proposed simulator can be widely applied to reliability analysis of 3D ICs under drop impact.Item Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network(Institute of Electrical and Electronics Engineers Inc., 2019-03-25) Zhang, S.; Lyu, W.; Yang, F.; Yan, C.; Zhou, Dian; Zeng, X.; Zhou, DianBayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. In the traditional Gaussian process regression model, the kernel functions are defined explicitly. The computational complexity of training is O(N³), and the computation complexity of prediction is O(N²), where N is the number of training data. Gaussian process model can also be derived from a weight space view, where the original data are mapped to feature space, and the kernel function is defined as the inner product of nonlinear features. In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. We use deep neural network to extract good feature representations, and then define Gaussian process using the extracted features. Model averaging method is applied to improve the quality of uncertainty prediction. Compared to Gaussian process model with explicitly defined kernel functions, the neural-network-based Gaussian process model can automatically learn a kernel function from data, which makes it possible to provide more accurate predictions and thus accelerate the follow-up optimization procedure. Also, the neural-network-based model has O(N) training time and constant prediction time. The efficiency of the proposed method has been verified by two real-world analog circuits. © 2019 EDAA.Item Multi-Objective Bayesian Optimization for Analog/RF Circuit Synthesis(Institute of Electrical and Electronics Engineers Inc.) Lyu, W.; Yang, F.; Yan, C.; Zhou, Dian; Zeng, X.; Zhou, DianIn this paper, a novel multi-objective Bayesian optimization method is proposed for the sizing of analog/RF circuits. The proposed approach follows the framework of Bayesian optimization to balance the exploitation and exploration. Gaussian processes (GP) are used as the online surrogate models for the multiple objective functions. The lower confidence bound (LCB) functions are taken as the acquisition functions to select the data point with best Pareto-dominance and diversity. A modified non-dominated sorting based evolutionary multi-objective algorithm is proposed to find the Pareto Front (PF) of the multiple LCB functions, and the next simulation point is chosen from the PF of the multiple LCB functions. Compared with the multi-objective evolutionary algorithms (MOEA) and the state-of-the-art online surrogate model based circuit optimization method, our method can better approximate the Pareto Front while significantly reduce the number of circuit simulations. © 2018 Association for Computing Machinery.Item Multi-Objective Bayesian Optimization for Analog/RF Circuit Synthesis(Institute of Electrical and Electronics Engineers Inc., 2019) Zeng, X.; Lyu, W.; Yang, F.; Yan, C.; Zhou, Dian; Zhou, DianIn this paper, a novel multi-objective Bayesian optimization method is proposed for the sizing of analog/RF circuits. The proposed approach follows the framework of Bayesian optimization to balance the exploitation and exploration. Gaussian processes (GP) are used as the online surrogate models for the multiple objective functions. The lower confidence bound (LCB) functions are taken as the acquisition functions to select the data point with best Pareto-dominance and diversity. A modified non-dominated sorting based evolutionary multi-objective algorithm is proposed to find the Pareto Front (PF) of the multiple LCB functions, and the next simulation point is chosen from the PF of the multiple LCB functions. Compared with the multi-objective evolutionary algorithms (MOEA) and the state-of-the-art online surrogate model based circuit optimization method, our method can better approximate the Pareto Front while significantly reduce the number of circuit simulations. © 2018 Association for Computing Machinery.Item Polystyrene-Coated Interdigitated Microelectrode Array to Detect Free Chlorine Towards IoT Applications(Japan Society for Analytical Chemistry, 2018-12-28) Liu, Y.; Liang, Yuchen; Xue, L.; Liu, R.; Tao, J.; Zhou, D.; Zeng, X.; Hu, Wenchuang (Walter); Liang, Yuchen; Hu, Wenchuang (Walter)We apply interdigitated microelectrode array (IDA) sensors for water quality monitoring. IDA sensors with an ion-sensitive coating show higher sensitivity of about 600 mV with the hypochlorite ion concentration increasing from 0 to 10 ppm more than the traditional sensing method. The response mechanism and selectivity have been studied. Several material components that affect the sensing process were explored. Coupling agents and plasticizer were introduced into the coating material to improve the coating material quality and its adhesion to the electrodes. The stability/repeatability and linearity have been significantly improved. ©2019, The Japan Society for Analytical Chemistry.Item Transforming Entity-Relationship Diagrams to Relational Schemas Using a Graph Grammar Formalism(Institute of Electrical and Electronics Engineers Inc., 2018-12) Liu, Y.; Zeng, X.; Zhang, Kang; Zou, Y.; 65983012 (Zhang, K); Zhang, KangAs a formal tool extended from string grammars, graph grammars provide an intuitive yet formal way to define and transform various visual languages. This paper proposes an approach to transform Entity-Relationship diagrams (E-R diagrams) to relational schemas using a graph grammar formalism. We briefly introduce the edge-based graph grammar, on which a set of productions is designed for specifying the syntax of E-R diagrams. The set of productions can be used to verify the validity of any given E-R diagram. In addition, a procedure of transforming a given E-R diagram to a relational schema is added into the parsing process. Via the graph grammar, the automatic transformation is rigorous yet concise. We finally provide an example E-R diagram for a business management system and its transformation into relational schemas to demonstrate the specification, transformation and analyzing the power of our approach. ©2018 IEEE.