Zhou, Dian
Permanent URI for this collectionhttps://hdl.handle.net/10735.1/6680
Dian Zhou joined the UT Dallas faculty in 1999 as a full professor in the Department of Electrical Engineering. His research interests include:
- High Speed and Low Power VLSI Circuits
- SoCs
- Analog IC Performance Optimization
- Silicon Biosensors
- CAD Tools and Algorithms
- Biomedical Electronics
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Browsing Zhou, Dian by Subject "Computer-aided design"
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Item A General Graph Based Pessimism Reduction Framework For Design Optimization Of Timing Closure(ACM) Peng, F.; Yan, C.; Feng, C.; Zheng, J.; Wang, S. -G; Zhou, Dian; Zeng, X.; Zhou, DianIn this paper, we develop a general pessimism reduction framework for design optimization of timing closure. Although the modified graph based timing analysis (mGBA) slack model can be readily formulated into a quadratic programming problem with constraints, the realistic difficulty is the size of the problem. A critical path selection scheme, a uniform sampling method with the sparse characteristics of the optimal solution, and a stochastic conjugate gradient method are proposed to accelerate the optimization solver. This modified GBA is embedded into design optimization of timing closure. Experimental results show that the proposed solver can achieve 13.82x speedup than gradient descent method with similar accuracy. With mGBA, the optimization of timing closure can achieve a better performance on area, leakage power, buffer counts.Item An Efficient Bayesian Yield Estimation Method for High Dimensional and High Sigma SRAM Circuits(Institute of Electrical and Electronics Engineers Inc.) Zhai, J.; Yan, C.; Wang, S. -G; Zhou, Dian; Zhou, DianWith increasing dimension of variation space and computational intensive circuit simulation, accurate and fast yield estimation of realistic SRAM chip remains a significant and complicated challenge. In this paper, du Experiment results show that the proposed method has an almost constant time complexity as the dimension increases, and gains 6x speedup over the state-of-the-art method in the 485D cases.Item Multi-Objective Bayesian Optimization for Analog/RF Circuit Synthesis(Institute of Electrical and Electronics Engineers Inc.) Lyu, W.; Yang, F.; Yan, C.; Zhou, Dian; Zeng, X.; Zhou, DianIn this paper, a novel multi-objective Bayesian optimization method is proposed for the sizing of analog/RF circuits. The proposed approach follows the framework of Bayesian optimization to balance the exploitation and exploration. Gaussian processes (GP) are used as the online surrogate models for the multiple objective functions. The lower confidence bound (LCB) functions are taken as the acquisition functions to select the data point with best Pareto-dominance and diversity. A modified non-dominated sorting based evolutionary multi-objective algorithm is proposed to find the Pareto Front (PF) of the multiple LCB functions, and the next simulation point is chosen from the PF of the multiple LCB functions. Compared with the multi-objective evolutionary algorithms (MOEA) and the state-of-the-art online surrogate model based circuit optimization method, our method can better approximate the Pareto Front while significantly reduce the number of circuit simulations. © 2018 Association for Computing Machinery.