Efficient Hardware Acceleration on SoC-FPGA using OpenCL
| dc.contributor.advisor | Schaefer, Benjamin Carrion | |
| dc.creator | Gogineni, Susmitha | |
| dc.creator.orcid | 0000-0002-9854-5441 | |
| dc.date.accessioned | 2018-03-22T18:43:41Z | |
| dc.date.available | 2018-03-22T18:43:41Z | |
| dc.date.created | 2017-12 | |
| dc.date.issued | 2017-12 | |
| dc.date.submitted | December 2017 | |
| dc.date.updated | 2018-03-22T18:43:41Z | |
| dc.description.abstract | Field Programmable Gate Arrays (FPGAs) are taking over the conventional processors in the field of High Performance computing. With the advent of FPGA architectures and High level synthesis tools, FPGAs can now be easily used to accelerate computationally intensive applications like, e.g., AI and Cognitive computing. One of the advantages of raising the level of hardware design abstraction is that multiple configurations with unique properties (i.e. area, performance and power) can be automatically generated without the need to re-write the input description. This is not possible when using traditional low-level hardware description languages like VHDL or Verilog. This thesis deals with this important topic and accelerates multiple computationally intensive applications amiable to hardware acceleration and proposes a fast heuristic Design Space Exploration method to find dominant design solutions quickly. In particular, in this work, we developed different computationally intensive applications in OpenCL and mapped them onto a heterogeneous SoC-FPGA. A Genetic Algorithm (GA) based meta-heuristics that does automatic Design Space Exploration (DSE) on these applications was also developed as GA has shown in the past to lead to good results in multi-objective optimization problems like this one. The developed explorer automatically inserts a set of control knobs into the OpenCL behavioral description, e.g., to control how to synthesize loops (unroll or not), and to replicate Compute Units (CUs). By tuning the these control attributes with possible values, thousands of different micro-architecture configurations can be obtained. Thus, an exhaustive search is not feasible and other heuristics are needed. Each configuration is compiled using Altera OpenCL SDK tool and executed on Terasic DE1-SoC FPGA board platform to record the corresponding performance and logic utilization. In order to measure the quality of the proposed GA-based heuristic, each application is explored exhaustively (taking multiple days to finish for smaller designs) to find the dominant optimal solutions (Pareto Optimal Designs). For complex and larger designs, exploring the entire design space exhaustively is not feasible due to very large design space. The comparison is quantified by using metrics like Dominance, Average Distance from Reference Set (ADRS) and run time speed up, showing that our proposed heuristics lead to very good results at a fraction of the time of the exhaustive search. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/10735.1/5662 | |
| dc.language.iso | en | |
| dc.rights | Copyright ©2017 is held by the author. Digital access to this material is made possible by the Eugene McDermott Library. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. | |
| dc.subject | Computer hardware description languages | |
| dc.subject | OpenCL (Computer program language) | |
| dc.subject | Field programmable gate arrays | |
| dc.subject | Systems on a chip | |
| dc.subject | Genetic algorithms | |
| dc.subject | Heuristic algorithms | |
| dc.title | Efficient Hardware Acceleration on SoC-FPGA using OpenCL | |
| dc.type | Thesis | |
| dc.type.material | text | |
| thesis.degree.department | Electrical Engineering | |
| thesis.degree.grantor | The University of Texas at Dallas | |
| thesis.degree.level | Masters | |
| thesis.degree.name | MSEE |