Browsing by Author "Makris, Yiorgos"
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Item Applications of Machine Learning in Test Cost Reduction and Quality Improvement(2019-12) Xanthopoulos, Konstantinos; Makris, YiorgosThe production of Integrated Circuits (ICs) is one of the most intricate processes currently performed in the world on such a large scale. Due to this complexity, process variations that are present in any manufacturing field, are intensified, resulting in compromising the main production goals, performance, reliability, and low cost. To combat the effects of process variations, multiple control steps have been introduced in the process at all stages, to test, filter, or re-calibrate the material produced. Despite considerable efforts to simultaneously attain all three goals of manufacturing, such solutions have not yet been established. Instead, depending on the product goals, only two of the goals are targeted, consequently compromising the third. In this work, we aim to study solutions where performance, reliability, and low cost can be reached simultaneously. To achieve this, we plan to utilize the plethora of data produced in all stages of the manufacturing process and at many granularity levels, allowing us to design adaptive machine learning-based solutions that counter the effects process variation has in the end result. Several studies will be presented, focusing on cost reduction for testing, which constitutes one of the major cost-bloating factors, and on improving the quality of tests performed. Each study is based on data provided by our industrial collaborators, thus supporting the practicality of the proposed solutions.Item Applications of Machine Learning in Test Cost Reduction, Yield Estimation and Fab-Of-Origin Attestation of Integrated Circuits(2017-05) Ahmadi, Ali; Makris, YiorgosThe semiconductor manufacturing industry is one of the most technologically advanced and cost-intensive industries. It has been a key driver for economic development and has powered the growth in computers, consumer electronics and the internet industry. Semiconductors are becoming indispensable in health-care, automobiles, defense and wireless communication. The rapidly growing and dynamically changing electronics market introduces interesting and complex challenges for semiconductor manufacturing companies. One such challenge is identifying production problems and increasing yield of integrated circuits (ICs), which is getting more difficult due to the complexity of new technology nodes. Another major challenge is the test cost that can be devoted to testing each die before it is shipped to a customer. This is important because continuous pressure for superior performance, along with intensified process variations in the latest technology nodes, have resulted in stringent limitations in the test cost. A most recent challenge in the semiconductor industry is security concerns regarding integrity of the electronics supply chain due to globalization and fab-less paradigm. To address these challenges, researchers have developed solutions based on statistical techniques and machine learning methods. The range of these solutions are from pre-silicon simulation-based methods to data analytic techniques that utilize post-silicon high-volume production data. In simulation-based domain, a rich dataset is available to examine and evaluate proposed solutions. However, these methods are very time-consuming and have a limited view of process statistics, as their grounding to silicon is established only through the variation models reflected in the process design kit (PDK). On the other hand, silicon-based learning methods are often impractical because of extra cost/overhead and new modifications in the production line. The aim of this work is to address these challenges and provide fast, accurate and feasible solutions using high-volume production data. More specifically, this dissertation introduces an adaptive test cost reduction method that successfully reduces the test cost significantly while abiding the industry principles in order to be readily deployable with minimal test operations support. A fast and accurate yield learning methodology is proposed to forecast high volume manufacturing (HVM) yield of a device based on production datasets from few engineering wafers. Finally, an advanced machine learning approach is proposed to attest the fabrication facility that manufactures a given IC.Item Applications of On-Die Neural Networks in Robust and Secure Analog/RF ICs and an Implementation in a Contemporary Technology(2020-08) Volanis, Georgios; Makris, YiorgosWhile manufactured ICs are subjected to extensive scrutiny in order to weed out defective or suspicious parts prior to their deployment, a variety of reasons such as silicon aging and adverse operational or environmental conditions might cause the performances of a previously healthy analog/RF IC to fail its design specifications. Similarly, field-activated triggers of hidden capabilities might cause a previously trusted analog/RF IC to exhibit malicious functionality. Additionally, prevention of unauthorized use of analog/RF ICs constitutes a major challenge in the field of hardware security. With analog/RF ICs now prevalent in most electronic systems, due to the rapid growth of wireless communications, sensor applications, and the Internet of Things (IoT), equipping them with post-deployment robustness, trustworthiness and performance locking mechanisms is very important. In this work, we demonstrate that on-die learning through an analog neural network can provide the aforementioned post-deployment capabilites. More specifically, the on-die neural network can be trained to (i) enhance robustness by calibrating the performances of an analog/RF IC, (ii) ensure trustworthiness by detecting the activation of potentially malicious circuitry, and/or (iii) prevent the unauthorized use of analog/RF ICs through performance locking. Based on the findings while implementing the three on-die learning tasks, we proceeded with the design, fabrication and fully characterization of an analog neural network in Globalfoundries’ 130nm RF CMOS process. Finally, all methods proposed in this dissertation have been verified with measurements from actual silicon chips.Item CAD Tools for PCB Reverse Engineering and IC Interconnect(2022-12-01T06:00:00.000Z) Nahar, Lubaba M; Sechen, Carl; Makris, Yiorgos; Anderson, William; Swartz, William; Friedman, JosephThis thesis will introduce two different CAD tools, MTBOM, and SMOR, for two specific applications. We developed our original tool, MTBOM, Metal Trace to Bill Of Materials automation for Printed Circuit Board Reverse Engineering (PCB-RE). Here, we assumed that the PCBs are devoid of any components or silkscreens, with only the wiring traces accessible on the various layers. This models the scenario where the PCBs are damaged and/or discarded. PCB-RE is highly useful for design verification and fault isolation of essential legacy systems, where it often happens that some parts in a legacy system are required to be replaced while there are no records in system documentation; MTBOM can offer a solution to such a situation identifying such parts by simply metal analysis. We demonstrate that our PCB-RE tool extracts the correct Bill of Materials (BoM) for ten different PCBs by analyzing primarily the metal layers. The proposed PCB-RE tool MTBOM detected every integrated circuit (IC) on the PCBs with no false positives or negatives. This scheme also identifies passive components, such as resistors, capacitors, and inductors. In SMOR, we have proposed a Simple Model Order Reduction approach for parasitic extrac- tions of metal interconnects. Parasitic EXtractions (PEX) of the metal interconnects are complex, consisting of millions or more passive elements. Consequently, the space requirements for PEX are enormous, and the simulation times are unacceptably long. The model order reduction method called PACT in Synopsys’ HSPICE simulator significantly reduces the simulation times. However, in SMOR, we have developed a simple technique to minimize each non-branching metal segment extraction to a single RC pi-element. And then, we can reduce the aggregate RC branches based on fundamental network analysis theorems. The effective delay to any number of projected nodes is modeled with the minimum number of RC components. When we applied SMOR on the C880 (an 8-bit ALU) ISCAS benchmark circuit for GF 12nm FinFET technology, it resulted in over a 10X reduction in R, and about 3X reduction in C size, while maintaining 100% delay accuracy and featuring approximately 3X speed up while applying on HSPICE and can make 73% speed up in simulation time while integrated with PACT compared to using PACT only. This dissertation presents MTBOM in its first three chapters, and we dedicate the last chapter to delivering SMOR.Item Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming(Institute of Electrical and Electronics Engineers Inc., 2019-03-25) Shihab, Mustafa M.; Tian, Jingxiang; Reddy, Gaurav Rajavendra; Hu, Bo; Swartz, William; Schaefer, Benjamin Carrion; Sechen, Carl; Makris, Yiorgos; 110195631 (Sechen, CM); Shihab, Mustafa M.; Tian, Jingxiang; Reddy, Gaurav Rajavendra; Hu, Bo; Swartz, William; Schaefer, Benjamin Carrion; Sechen, Carl; Makris, YiorgosWidespread adoption of the fabless business model and utilization of third-party foundries have increased the exposure of sensitive designs to security threats such as intellectual property (IP) theft and integrated circuit (IC) counterfeiting. As a result, concerted interest in various design obfuscation schemes for deterring reverse engineering and/or unauthorized reproduction and usage of ICs has surfaced. To this end, in this paper we present a novel mechanism for structurally obfuscating sensitive parts of a design through post-fabrication TRAnsistor-level Programming (TRAP). We introduce a transistor-level programmable fabric and we discuss its unique advantages towards design obfuscation, as well as a customized CAD framework for seamlessly integrating this fabric in an ASIC design flow. We theoretically analyze the complexity of attacking TRAP-obfuscated designs through both brute-force and intelligent SAT-based attacks and we present a silicon implementation of a platform for experimenting with TRAP. Effectiveness of the proposed method is evaluated through selective obfuscation of various modules of a modern microprocessor design. Results corroborate that, as compared to an FPGA implementation, TRAP-based obfuscation offers superior resistance against both brute-force and oracle-guided SAT attacks, while incurring an order of magnitude less area, power and delay overhead. © 2019 EDAA.Item Design Space Exploration for Secure and Power-efficient Microprocessor Designs(2019-11-21) Zaman, Monir Mohammad; Makris, YiorgosWith increasing reliance on third-party, potentially untrusted fabrication facilities designers face increasing threat of intellectual property (IP) piracy in the form of reverse-engineering, over-production, hardware Trojans insertion etc. In this work, we propose performance locking, a variant of logic locking technique, to thwart aforementioned attacks. In the proposed provably-secure performance locking scheme, we carefully integrate additional logic into the design and protect the modified design using a secure key. Performance locking takes advantage of the design’s control and data path, and inserts additional bubbles in the pipeline when an unauthorized user tries to access the system. The locking scheme has been implemented in multiple microprocessor pipelines and effectiveness of the locking is demonstrated through register transfer level (RTL) simulation and field programmable gate array (FPGA) implementation. Our simulation results show a ∼97% performance degradation in the locked design as compared to its original version. We also evaluate trade-offs between performance, runtime, and power/area overhead for the proposed scheme. While exploring performance locking’s impact on power consumption we observed that, the state-of-the-art power estimation method is not sufficiently accurate. Specifically, the inaccuracies stem from the simplistic modeling of the design at the early stage. To this end, we present a novel a Cross-layer frAmework for accurate Power Estimation (CAPE). CAPE implements an intelligent integration of system-level and RT-level performance parameters for estimating power consumption. We propose two different approaches for the CAPE framework. Using real-life workloads, the simulation results show a 9% accuracy improvement over the state-of-the-art method of power estimation at early design stage.Item Enabling CAD Support for the Field Programmable Transistor Array(2019-08) Ramanidharan, Bharath; 0000-0001-7117-2422 (Ramanidharan, B); Makris, YiorgosThis thesis concerns the development and verification of a CAD flow for a Field Programmable Transistor Array, that eases the task of creating and implementing a bit stream for the FPTA. The CAD flow takes in the behavioral Verilog file as the input and produces the bit stream. Two case studies have been explained in the thesis, also a setup which is required to load in this bit stream into the FPTA hardware has been described. This helps to implement any digital design in the FPTA hardware and test the result giving inputs directly from a PC and reading out the outputs.Item Ensuring Hardware Robustness via Security Verification(December 2023) Meng, Xingyu 1993-; Basu, Kanad; Schmidtke, David; Bhatia, Dinesh; Makris, Yiorgos; Saquib, MohammadSystem-on-Chips (SoCs) play a pivotal role in modern computing systems, integrating multiple Intellectual Property (IP) cores to deliver diverse functionalities. However, this integration presents unique security challenges that can result in vulnerabilities escaping the verification phase and becoming potential exploits. Moreover, the integration of commercial off-the-shelf (COTS) components into system designs provides cost-effective solutions but introduces the risk of hidden malicious hardware. On the other hand, asynchronous events in complex SoC design introduce challenges for security verification. Furthermore, Network-on-Chip (NoC) architectures introduce new vulnerabilities during message transmission across on-chip networks. Although security properties are introduced to address these vulnerabilities, generating security properties for SoCs can be a daunting task, typically requiring extensive developer expertise and time. This dissertation extends and explores various approaches to current hardware verification in multiple aspects. First, we introduce RTL-ConTest, a Register Transfer Level (RTL) security vulnerability detection algorithm, that extracts critical process flows from a design and executes RTL-level Concolic testing to generate security test cases for identifying critical exploits. Second, we address the asynchronous resets by extending the concept of control flow graph (CFG) and extraction of reset-controlled events while avoiding combinatorial explosion. Third, by utilizing CFG extraction and security properties, we develop a framework for systematic detection of security violations in NoC designs resulting from vulnerabilities in NoC communication through formal state exploration. Fourth, We propose an information tracking framework to identify potential information flow violations in COTS integrated circuits by analyzing their designs and demonstrating their effectiveness in experimental results. Lastly, we introduce a language-based machine-learning framework that extracts essential security information from processor documentation and converts them into security constraints at the RTL level, enhancing the robustness and efficiency of security property generation.Item Hardware Trojans in Wireless Cryptographic ICs(2017-05) Liu, Yu; Makris, YiorgosOver the last decade, the problem of hardware Trojans in manufactured integrated circuits (ICs) has been a topic of intense investigation by academic researchers and governmental entities. Hardware Trojans are malicious modifications introduced in a manufactured IC, which can be exploited by a knowledgeable adversary to cause incorrect results, steal sensitive data, or even incapacitate a chip. Given the sensitive nature of applications wherein hardware Trojan-infested ICs may be deployed, developing detection methodologies has become paramount. Indeed, traditional test methods fall short in revealing hardware Trojans, as they are geared towards identifying modeled defects and, therefore, cannot reveal unmodeled malicious inclusions. Various hardware Trojan detection methods have been proposed, most of them targeted digital circuits. As pointed out therein, the Analog/RF domain is an attractive attack target, since the wireless communication of these chips with the environment over public channels simplifies the process of staging an attack without obtaining physical access to the I/O of the chip. On the other hand, signals in an Analog/RF IC are continuous and highly-correlated to one another; hence, the likelihood of a modification disturbing these correlations is very high. Therefore, this dissertation outlines the problems and proposes three solutions to ensure trustworthiness of Analog/RF ICs: namely, i) Utilize statistical side channel fingerprinting to detect hardware Trojan in Analog/RF ICs. ii) Propose to use a combination of a trusted simulation model, measurements from process control monitors (PCMs), that are typically present either on die or on wafer kerf, and advanced statistical tail modeling techniques to detect hardware Trojan without relying on golden chips. iii) Introduce a concurrent hardware Trojan detection (CHTD) methodology for wireless cryptographic integrated circuits (ICs), based on continuous extraction of a side-channel fingerprint and evaluation by a trained on-chip neural classifier. All methods proposed in this dissertation have been verified with measurements from actual silicon chips.Item Hardware Trojans in Wireless Networks(2018-08) Subramani, Kiruba Sankaran; Makris, Yiorgos; Nosratinia, AriaThe area of hardware security has received intense scrutiny in recent years due to outsourcing of semiconductor device manufacturing, use of third party Intellectual Properties (IPs) in the fabricated design, Electronic Design Automation (EDA) tools and software from different vendors, etc. Therefore, there is a general notion that the IC supply chain isn’t as secure as it used to be. This problem is further aggravated by the fact that the cost of having a fully trusted supply chain is too expensive. As a result, government entities, the semiconductor industry and academic groups have spent a lot of time and effort to secure the IC supply chain. Over the past decade, the area of hardware security has seen a lot of research activity, mainly focusing on the digital domain, addressing the design and development of secure microprocessors. However, little has been done in the Analog/RF design space including wireless networks. Therefore, in this research work, security vulnerabilities in wireless networks are explored, covering a broad design space spanning from the baseband to the Analog/RF front-end of a wireless device. The proposed approach is to first develop a metric to quantify the hardware Trojan threat in wireless devices. Next, the design space in a wireless device is explored to identify blocks that possess vulnerabilities that can be represented in terms of the defined metric. For each of the identified vulnerabilities, a theoretical analysis of the hardware Trojan threat is performed, followed by simulation and experimental evaluation of the Trojan’s impact on a user communication link. Accordingly, Trojan-agnostic defense techniques are developed to prevent these classes of hardware Trojan attacks and their effectiveness is evaluated under practical operating conditions.Item Hardware-based Malware Detection in Modern Microprocessors: Formal and Statistical Methods in System-level Security Assurance(May 2023) Zhang, Yunjie; Haas, Zygmunt; Makris, Yiorgos; Basu, Kanad; Hamlen, Kevin; Carrion Schaefer, BenjaminPrevious studies in workload forensics have relied on retrospective assessments using comprehensive process execution profiles, hindering the ability to take prompt action against ongoing cyber threats. In this dissertation, we put forth a hardware-centric approach for real-time workload forensics, enabling the identification of processes during their execution. We present a universal framework that formalizes real-time forensic analysis and malware detection procedures, incorporating hardware-level feature extraction and machine learning- based data analysis. To showcase the effectiveness of our proposed framework, we explore hardware-based workload forensics and hardware-based Spectre attack detection. Our experimental findings indicate that our system can successfully identify Spectre attacks across thirteen intentionally vulnerable victim code patterns. Beyond machine learning techniques, we also utilize formal analysis to ensure the secure execution of machine-level binaries on specific hardware configurations. This method offers a more extensive coverage of the state space compared to verification techniques dependent on testbenches, potentially encompassing the entire state space.Item Hardware-Based Workload Forensics and Malware Detection in Modern Microprocessors(2018-12) Zhou, Liwei; Makris, YiorgosTraditional computer forensics and/or malware detection methods are generally implemented at the operating system (OS) or the hypervisor level, which benefits from abundant software semantics and implementation flexibility. Nevertheless, the data logging and monitoring systems involved in these methods are vulnerable to spoofing attacks at the same level, which undermine their effectiveness. In this dissertation, the hardware-based methodologies are proposed to perform workload forensics and/or malware detection in microprocessors. In contrast to the software-based counterparts, a hardware-based implementation ensures the immunity to software tampering. Specifically, a generic architecture is introduced which a hardware-based forensic analysis or a malware detection method needs to follow, as well as the various architecture-level information which could potentially be harnessed to ensure system security and/or integrity. To illustrate the proposed concept, two incarnations, i.e., hardware-based workload forensics and hardware-based rootkit detection are present. Experimental results corroborate that even a low-cost hardware implementation can facilitate highly successful forensics analysis and/or malware detection, while taking advantage of its innate immunity to software-based attacks.Item IC Laser Trimming Speed-up Through Wafer-Level Spatial Correlation Modeling(2019-12) Xanthopoulos, Konstantinos; Makris, YiorgosLaser trimming is used extensively to ensure accurate values of on-chip precision resistors in the presence of process variations. Such laser resistor trimming is slow and expensive, typically performed in a closed-loop, where the laser is iteratively fired and some circuit parameter (i.e. current) is monitored until a target condition is satisfied. Toward reducing this cost, we introduce a novel methodology for predicting the laser trim length, thereby eliminating the closed-loop control and speeding up the process. Predictions are obtained from wafer-level spatial correlation models, learned from a sparse sample of die on which traditional trimming is performed. Effectiveness is demonstrated on an actual wafer of lasertrimmed ICs.Item Intellectual Property Protection Using a Transistor-level Programmable Fabric(2021-12-01T06:00:00.000Z) Shihab, Mustafa Munawar; Desmedt, Yvo G.; Makris, Yiorgos; Sechen, Carl; Carrion Schaefer, Benjamin; Swartz, WilliamOver the years, the semiconductor industry has followed the overarching economic trend of globalization and offshore manufacturing. While the widespread utilization of third-party foundries has helped design houses lower manufacturing costs, it has also exposed their products to security threats such as intellectual property (IP) theft and integrated circuit (IC) counterfeiting. Therefore, the ability to hide sensitive designs from a potentially untrusted foundry is becoming paramount for IP protection. In response, the research community has proposed various design obfuscation solutions for thwarting reverse-engineering and unauthorized reproduction/usage of ICs. Unfortunately, while the state-of-the-art design obfuscation schemes can offer protection against brute-force attacks, they remain vulnerable to intelligent attacks, such as ones that leverage a Boolean Satisfiability (SAT) solver. In this work, we present a novel IP protection methodology for structurally obfuscating sensitive parts of a design through pre-fabrication omission and post-fabrication programming. We introduce a transistor-level programmable (TRAP) fabric tailored to replace portions of an ASIC design for our obfuscation purposes. Unfortunately, the state-of-theart computer-aided design (CAD) tools and testing solutions are designed for conventional application-specific ICs (ASICs) and field-programmable gate arrays (FPGAs) and cannot support the new architecture. To this end, we develop the ancillary ancillary infrastructure required for practical adoption of the TRAP fabric. Specifically, we present a full-stack CAD solution that takes an RTL description as input, performs synthesis, placement, routing, and finally generates the bitstream to program the design on a TRAP fabric. We also propose a novel application-agnostic test methodology for TRAP, which consists of a multi-phase, cascadable scheme to efficiently test the programmable transistors, the built-in gates, and the interconnect network in the fabric. We then theoretically analyze the complexity of attacking TRAP-obfuscated designs through both brute-force and intelligent SAT-based attacks. Finally, we present a hardware testbed for experimenting with TRAP and evaluate the efficacy of the proposed method through selective obfuscation of various benchmark circuits and two modern microprocessor designs. Our results corroborate that, as compared to an FPGA implementation, TRAP-based obfuscation offers superior resistance against both brute-force and oracle-guided SAT attacks while incurring an order of magnitude less area, power, and delay overhead.Item Low Noise Integrated Circuits and Systems Using Nano-Scale MOSFETs and Intelligent Post-Fabrication Selection(December 2021) Yelleswarapu, Venkata Pavan Kumar; O, Kenneth K.; Venkatesan, Subbarayan; Henderson, Rashaunda; Ma, Donsheng Brian; Makris, YiorgosRecent advances in integrated radio design have enabled many applications such as wearable healthcare, 5G communication, and beyond 5G or 6G applications for ultra-high data rate communications, high-resolution imaging, sensing, and spectroscopy. All these applications require low noise radio transceivers for achieving high performance. For example, applications requiring high data rate and higher order modulation schemes need to achieve high signal to noise ratio (SNR) and therefore a low noise figure to maintain a low bit-error rate (BER). In addition, noise phenomena like jitter and phase noise can impact the critical parameters like maximum achievable data rate and energy efficiency. This research aims to improve the noise performance of integrated circuits and systems through intelligent post-fabrication selection of an array of nanoscale transistors sized near the minimum in CMOS processes. A phase noise reduction technique in LC Voltage Controlled Oscillators (VCO’s) is demonstrated by post-fabrication selection of a subset of an array of near minimum-size cross-coupled transistor pairs with reduced low frequency noise and thermal noise. The technique reduces the phase noise by taking advantage of the fact that when transistor dimensions are reduced, the low frequency noise and thermal noise vary significantly. Applying an intelligent post-fabrication selection process using a genetic algorithm, the lowest phase noise of -122 dBc/Hz, -127 dBc/Hz, -137.5 dBc/Hz at 600-kHz, 1-MHz, and 3-MHz offsets, respectively from a 3.8-GHz carrier has been measured. The VCO prototype was fabricated in a 65-nm CMOS process and dissipates 7 mW of DC power. The maximum figure of merit (FoM) including phase noise, carrier frequency and power consumption is 191 dBc/Hz and the figure of merit including the VCO core area, FoMA is 207 dBc/Hz. A technique is demonstrated to reduce both the in-band and out-of-band phase noise of a 4-GHz Integer-N PLL by employing an array of individually selectable cross-coupled pairs formed using near minimum-size transistors in an LC VCO and intelligent post-fabrication selection. By reducing both the in-band and out-of-band phase noise, the overall integrated phase jitter in a frequency synthesizer can be minimized. Applying an intelligent post-fabrication selection process, the lowest phase noise of -72 dBc/Hz at 30-kHz offset, -106 dBc/Hz at 300-kHz offset, -121.8 dBc/Hz at 1-MHz offset, and -132.5 dBc/Hz at 3-MHz offset, respectively from a 4.01-GHz locked carrier has been measured. The integrated rms jitter from 100-kHz to 100-MHz offsets is 440 fs. A mixer-first downconverter employing an array of passive mixers formed using near minimumsize transistors and intelligent post-fabrication selection achieves a double sideband noise figure of 4.2 dB at RF of 6 GHz, which is the lowest at 6 GHz for CMOS mixer-first downconverters. The downconverter is fabricated in 65-nm CMOS and demonstrates out-of-band IIP3 and IIP2 of 25 dBm and 65 dBm, respectively at 80-MHz IF, while dissipating 11.5 mW. Post-fabrication selection is performed by a genetic algorithm which takes ~17 generations to converge to the combinations exhibiting the lowest noise.Item Machine Learning-Based Hotspot Detection: Fallacies, Pitfalls and Marching Orders(2020-04-09) Rajavendra Reddy, Gaurav; Makris, YiorgosExtensive technology scaling has not only increased the complexity of Integrated Circuit (IC) fabrication but also multiplied the challenges in the Design For Manufacturability (DFM) space. Among these challenges, detection of design weak-points, popularly known as Lithographic Hotspots, has attracted substantial attention. Hotspots are certain patterns which exhibit a higher probability of causing defects due to complex design-process interactions. Identifying such patterns and fixing them in the design stage itself is imperative towards ensuring high yield. In the early days of hotspot detection, Pattern Matching (PM) based methods were proposed. While effective in identifying previously known patterns, these methods failed to identify Never-Seen-Before (NSB) hotspots. To address this drawback, Machine Learning (ML) based solutions were introduced. Over the last decade, we have witnessed a plethora of ML-based hotspot detection methods being developed, each slightly outperforming its predecessors in accuracy and false-alarm rates. In this work, we critically analyze the ML-based hotspot detection literature and we highlight common fallacies which are found therein. We pinpoint the pitfalls in the ICCAD-2012 benchmarks that have led to these fallacies. We propose an enhanced version of this benchmark dataset, titled ICCAD-2019 benchmarks, which we deem more appropriate for accurately assessing hotspot detection methods. We offer our best recommendations /marching orders to improve the effectiveness of ML-based hotspot detection methods and experimentally demonstrate the effectiveness of the proposed methods in comparison to the stateof-the-art. Furthermore, we perform the first ever silicon validation of hotspots, wherein, we fabricate several hotspot patterns on silicon, study their electrical characteristics and propose a methodology to rank them. Through Early Design Space Exploration (EDSE), we also perform the first quantitative demonstration of early hotspot detection and TrulyNever-Seen-Before (TNSB) hotspot detection.Item Machine Learning-based Solutions for Comprehending and Mitigating Imperfections of Semiconductor Manufacturing and Testing(2022-12-01T06:00:00.000Z) Neethirajan, Deepika; Makris, Yiorgos; Rodrigues, Danieli; Henderson, Rashaunda; Nourani, Mehrdad; Friedman, JosephIn recent years, significant technological advancements have been made in the semiconductor industry; However, with these advancements, comes a lot of manufacturing and testing challenges that have a direct impact on the cost and yield of the overall outcome. While advanced technology nodes enable production of more powerful devices that have a smaller form factor, operation of such devices is more susceptible to process variations. To address the impacts of process variations without impacting the performance of devices, manufacturers employ post-silicon calibration techniques. One major pitfall of post-silicon calibration is the need to perform numerous test measurements and adjustments that significantly contribute towards the overall test time, thereby hindering the profit margins of new products. Along with the minimal cost expectations, there are higher quality expectations in terms of extremely low number of defects. This results in implementing exhaustive and contemporary test solutions that result in a non-negligible amount of good devices being discarded. In this work, several machine learning-based solutions are proposed to address the increasing test costs and to recover some of the yield loss. An adaptive test cost reduction technique is proposed to identify the optimal operating voltage for a High-Volume Manufacturing (HVM) device, by taking advantage of the correlation that exists between different test measurements and operating voltages. Another test cost reduction technique was proposed to enable testing a device across multiple temperature corners, where the current testing process is extremely time consuming and expensive. Towards addressing the problem of impairments that affect the performance of Radio Frequency (RF) transmitters due to process variations, a machine- learning based solution was proposed to classify and decompose the RF impairments. The model leverages unique signatures left by the impairments on the transmitted signal constellation points. Towards recovering yield loss caused by using conservative test programs that help achieve higher quality expectations, a machine learning based solution was proposed, which exploits the statistical correlation between two key groups of tests currently performed for these devices. Finally, to avoid die damage that occurs due to misalignment of the blades used in the wafer dicing equipment, a machine learning-based solution was proposed that takes advantage of the acoustic emissions recorded by the dicing equipment. All the proposed solutions have been evaluated using dataset provided by our industry liaisons and the results are shown in this work.Item Proof-Carrying Hardware Intellectual Property (PCHIP): Framework Automation and Enhancement(2018-08) Bidmeshki, Mohammad Mahdi; Makris, YiorgosProof carrying hardware intellectual property (PCHIP) introduces a framework in which a hardware intellectual property (IP) is accompanied by formal proofs of certain security-related properties, ensuring that the acquired IP is trustworthy. PCHIP framework adds extra burdensome tasks in the hardware IP development process, hindering its wide acceptance by the hardware design community. This work presents efforts toward automating parts of the PCHIP framework, in order to simplify the adoption of PCHIP by hardware designers, IP developers, and IP consumers and, thereby, increasing trust in hardware designs and hardware IP acquisition. It also demonstrates efforts in enhancing the PCHIP framework with more capabilities, including hierarchical proof development, hybrid module libraries which contain proved lemmas, in addition to the hardware module delivered as code in a hardware description language (HDL), and information flow tracking (IFT) in analog, digital and mixed-signal designs.Item Routing Methods for Transistor-level Programmable Fabrics(2022-12-01T06:00:00.000Z) Xu, Xiangyu; Makris, Yiorgos; Sechen, Carl M.; Hamlen, Kevin; Hamlen, Kevin; Hamlen, Kevin; Hamlen, Kevin; Swartz, William (Bill); Carrion Schaefer, BenjaminYou may be surprised if someone tells you that chips are the new oil. Economic historian Chris Miller, in his new book Chip War, states that chips are the world’s most critical resource, and explains how the semiconductor came to play a critical role in modern life. Today, military, economic, and geopolitical power are built on a foundation of chips. In many ways, our world is “built” on semiconductors. As the impact of digital on lives and businesses has accelerated, semiconductor markets have boomed, with sales growing by more than 20 percent to about $600 billion in 2021. McKinsey [1] analysis based on a range of macroeconomic assumptions suggests the industry’s aggregate annual growth could average from 6 to 8 percent a year up to 2030. The result? A $1 trillion dollar industry by the end of the decade, assuming average price increases of about 2 percent a year and a return to balanced supply and demand after current volatility. The semiconductor industry has evolved over the past few decades in all fields, specifically chip design, manufacture, packaging and testing. The chip design methodology has also advanced with the continuous scaling of the feature size in Very Large Scale Integrated circuits (VLSI). The tiny chips are one of the most difficult devices to design in the world, following a fairly long chip design flow, all design flow steps are necessary and equally important; if mistakes are introduced in any step, this may make the whole chip unable to work as expected. Among those numerous steps, routing is to connect all components in the circuit together properly and efficiently. Programmable logic devices, such as Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLDs), have grown in popularity in a myriad of applications since their inception due to their reconfigurability and lower non-recurrent engineering costs when compared to Application Specific Integrated Circuits (ASICs). To keep pace with growing application needs and process technology improvements, FPGAs have traditionally chosen full custom chip design approaches. However, embedded FPGAs (eFPGAs) have been introduced to enable ASICs to be less application specific, thereby producing the need for an agile design approach to accelerate the eFPGA design process. A TRAnsistor-level Programmable fabric (TRAP) has received interest recently as a more compact eFPGA for hardware obfuscation, in which a selected sensitive portion of the design is implemented in the eFPGA, and the residue is implemented as ASIC. Unfortunately, state-of-the-art routing tools are not fully compatible with the new architecture. In this work, we develop routing methods customized for the TRAP fabric, to address all the unique architecture requirements. Experimental results corroborate that the proposed routing methods for the transistor-level programmable fabric are working as needed and are fully automated with a single push-button solution.Item Secrecy and covertness in the presence of multi-casting, channel state information, and cooperative jamming(2021-12-01T06:00:00.000Z) ZivariFard, Hassan; Nosratinia, Aria; Bloch, Matthieu R.; Fischetti, Massimo V.; Fonseka, John P.; Makris, Yiorgos; Minn, HlaingWe study secret communication over multi-transmitter multicast problem in the presence of an eavesdropper, wherein weak and strong secrecy regimes are studied. For the weak secrecy regime, the method of Chia and El Gamal is extended to two transmitters. We show that the achievable region calculated for the weak secrecy regime in this channel configuration is no bigger than the one calculated under strong secrecy. Two examples are presented in which the inner and outer bounds of secrecy region meet. In the process, we also characterize the minimum amount of randomness necessary to achieve secrecy in the multiple-access wiretap channel. We consider the problem of covert communication over a state-dependent channel when the Channel State Information (CSI) is available either non-causally, causally, or strictly causally, either at the transmitter alone, or at both transmitter and receiver. In contrast to previous work, we do not assume the availability of a large shared key at the transmitter and legitimate receiver. Instead, we only require a secret key with negligible rate to bootstrap the communication and our scheme extracts shared randomness from the CSI in a manner that keeps it secret from the warden, despite the influence of the CSI on the warden’s output. When CSI is available at the transmitter and receiver, we derive the covert capacity region. When CSI is only available at the transmitter, we derive inner and outer bounds on the covert capacity. We also provide examples for which the covert capacity is positive with knowledge of CSI but is zero without it. We consider the problem of covert communication in the presence of a cooperative jammer. It is known that in general, a transmitter and a receiver can communicate only O( √ n) covert bits over n channel uses, i.e., zero rate. Here, we show that a cooperative jammer can facilitate the communication of positive covert rates, subject to the presence of friendly jammer in the environment. We consider various scenarios in which it is possible to achieve positive rate for covert communication. For these scenarios, we derive inner and outer bounds on the covert capacity region, and also we characterize the covert capacity region for some of these scenarios.